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參數(shù)資料
| 型號： | 74HC7404 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 5位× 64字FIFO寄存器，三態(tài) |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 74HC7404 |
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September 1993
15
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Notes to
Fig.10
1.
2.
3.
4.
DOR HIGH; no data transfer in progress, valid data is present at output stage
SO set HIGH; results in DOR going LOW
DOR goes LOW; output stage “busy”
SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
Repeat process to unload the 3rd through to the 64th word from FIFO.
DOR remains LOW; FIFO is empty.
5.
6.
7.
Fig.10 Waveforms showing the SO input to DOR output propagation delay, the SO pulse widths and maximum
pulse frequency.
handbook, full pagewidth
MGA661
VM
(1)
SO INPUT
Qn OUTPUT
1/
fmax
W
t
DOR OUTPUT
tPHL
tPLH
VM
(1)
VM
(1)
1st SO pulse
2nd SO pulse
64th SO pulse
1st word
2nd word
64th word
7
3
1
5
6
4
2
(1) HC
:
V
M
= 50%; V
I
= GND to V
.
V
M
= 1.3 V; V
I
= GND to 3 V.
HCT :
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