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參數(shù)資料
| 型號(hào)： | 74HC195 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit parallel access shift register |
| 中文描述： | 4位并行存取移位寄存器 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 67K |
| 代理商： | 74HC195 |
December 1990
8
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
AC WAVEFORMS
Fig.6
Waveforms showing the clock (CP) to
output (Q
n
) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the master reset
(MR) pulse width, the master reset to output
(Q
n
) propagation delays and the master
reset to clock (CP) removal time
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.8
Waveforms showing the data set-up
and hold times for J, K and D
n
inputs.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
Fig.9
Waveforms showing the set-up and hold
times from the parallel enable input
(PE) to the clock (CP).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3V; V
I
= GND to 3 V.
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