參數(shù)資料
型號(hào): 74HC08
廠商: ON SEMICONDUCTOR
英文描述: Quad 2-Input AND Gate(四2輸入與門)
中文描述: 四2輸入與門(四2輸入與門)
文件頁(yè)數(shù): 3/7頁(yè)
文件大?。?/td> 121K
代理商: 74HC08
74HC08
http://onsemi.com
3
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
(V)
Guaranteed Limit
Symbol
Parameter
Condition
55 to 25
°
C
85
°
C
125
°
C
Unit
V
IH
Minimum High
Level Input Voltage
V
out
= 0.1V or V
CC
0.1V
|I
out
|
20 A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low
Level Input Voltage
V
out
= 0.1V or V
CC
0.1V
|I
out
|
20 A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High
Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
IH
or V
IL
|I
out
|
2.4mA
|I
out
|
4.0mA
|I
out
|
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low
Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
20 A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
|
2.4mA
|I
out
|
4.0mA
|I
out
|
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current
V
in
= V
CC
or GND
6.0
±
0.1
±
1.0
±
1.0
A
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 A
6.0
2.0
20
40
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High
Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 6ns)
V
CC
(V)
Guaranteed Limit
Symbol
Parameter
55 to 25
°
C
85
°
C
125
°
C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High
Speed CMOS Data Book (DL129/D).
10
10
10
pF
C
PD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no
load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High
Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, V
CC
= 5.0 V, V
EE
= 0 V
pF
20
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