參數(shù)資料
型號(hào): 74F846
廠商: NXP Semiconductors N.V.
英文描述: 8-bit bus interface latches, inverting (3-State)(8位總線接口鎖存器,反相(三態(tài)))
中文描述: 8位總線接口龍頭,反相(3態(tài))(8位總線接口鎖存器,反相(三態(tài)))
文件頁數(shù): 14/18頁
文件大?。?/td> 206K
代理商: 74F846
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
14
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
V
M
V
M
V
M
t
PHL
t
PLH
Dn, LE
Qn
SF01303
Waveform 1. Propagation Delay, Non-Inverting Path
V
M
V
M
V
M
V
M
t
PLH
t
PHL
Dn, LE
Qn
SF01304
Waveform 2. Propagation Delay, Inverting Path
LE
V
M
V
M
PRE,
MR
V
M
t
w
(L)
t
REC
V
M
V
M
t
PLH
t
PHL
Qn, Qn
Qn, Qn
SF01305
Waveform 3. Master Reset and Preset Pulse Width,
Master Reset and Preset to Output Delay,
and Master Reset and Preset to Latch Enable Recovery Time
t
h
(H)
t
s
(H)
LE
V
M
V
M
V
M
V
M
V
M
V
M
t
h
(L)
t
s
(L)
Dn
V
M
t
w
(H)
SF01306
Waveform 4. Data Setup and Hold Times
V
M
V
M
V
M
t
PHZ
t
PZH
OEn
V
OH
-0.3V
0V
Qn, Qn
SF00509
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
M
V
M
V
M
t
PLZ
t
PZL
V
OL
+0.3V
3.5V
OEn
Qn, Qn
SF00510
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable time from Low Level
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