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參數(shù)資料
| 型號(hào)： | 74F846 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit bus interface latches, inverting (3-State)(8位總線(xiàn)接口鎖存器，反相（三態(tài)）) |
| 中文描述： | 8位總線(xiàn)接口龍頭，反相（3態(tài)）（8位總線(xiàn)接口鎖存器，反相（三態(tài)）） |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大小： | 206K |
| 代理商： | 74F846 |
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Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
1999 Jun 23
10
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
MIN
TYP
2
MAX
= 15mA
I
OH
= –15mA
±
10%V
CC
2.2
V
V
OH
High level output voltage
High-level output voltage
V
= MIN,
V
IL
= MAX, V
IH
= MIN
±
5%V
CC
2.2
3.3
V
,
= 24mA
I
OH
= –24mA
±
10%V
CC
2.0
V
±
5%V
CC
2.0
V
V
OL
Low level output voltage
Low-level output voltage
V
= MIN,
V
IL
= MAX, V
IH
= MIN
I
OL
= 32mA
±
10%V
CC
0.38
0.55
V
,
I
OL
= 48mA
±
5%V
CC
0.38
0.55
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
–0.73
–1.2
V
I
I
Input current at maximum input voltage
V
CC
= 0.0V, V
I
= 7.0V
100
μ
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
μ
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
–20
μ
A
I
OZH
Off-state output current,
High-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off-state output current,
Low-level voltage applied
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
Short-circuit output current
3
V
CC
= MAX
–100
–225
mA
I
CCH
50
65
mA
74F841
I
CCL
V
CC
= MAX
60
80
mA
I
CCZ
70
92
mA
I
CCH
40
60
mA
74F842
I
CCL
V
CC
= MAX
65
90
mA
I
CC
Supply current
(total)
I
CCZ
60
90
mA
I
CCH
65
90
mA
74F843
74F845
I
CCL
V
CC
= MAX
75
100
mA
I
CCZ
85
115
mA
I
CCH
50
70
mA
74F846
I
CCL
V
CC
= MAX
70
95
mA
I
CCZ
70
95
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I
OS
tests should be performed last.
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