參數(shù)資料
型號(hào): 74F835
廠商: NXP Semiconductors N.V.
英文描述: 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out
中文描述: 8位的移位寄存器的2:1多路復(fù)用器,在鎖定的“B”的投入,串行輸出,
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 61K
代理商: 74F835
Philips Semiconductors
Product specification
74F835
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
1990 Jan 08
5
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
UNIT
T
amb
= +25
°
C
V
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
°
C to +70
°
C
V
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
130
150
100
MHz
Propagation delay
CP to Q7 (Load)
Waveform 1
5.0
5.0
7.0
7.0
9.5
9.5
5.0
5.0
10.0
10.0
ns
Propagation delay
CP to Q7 (Shift)
Waveform 1
5.0
5.0
7.0
7.0
9.5
9.5
5.0
5.0
10.0
10.0
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
UNIT
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time
DnA or DnB to CP
Waveform 2
3.5
3.5
3.5
3.5
ns
Hold time
DnA or DnB to CP
Waveform 2
1.0
1.0
1.5
1.5
ns
Setup time
DS to CP
Waveform 2
1.0
1.0
1.5
1.5
ns
Hold time
DS to CP
Waveform 2
2.0
2.0
2.5
2.5
ns
Setup time
PE to CP
Waveform 2
3.5
3.5
4.0
4.0
ns
Hold time
PE to CP
Waveform 2
0.0
0.0
0.0
0.0
ns
Setup time
DnB to LE
Waveform 2
0.0
0.0
0.0
0.0
ns
Hold time
DnB to LE
Waveform 2
3.0
3.0
4.0
4.0
ns
Setup time
SA/B to CP
Waveform 2
4.5
4.5
5.0
5.0
ns
Hold time
SA/B to CP
Waveform 2
0.0
0.0
0.0
0.0
ns
clock pulse width,
High or Low
Waveform 1
4.5
4.5
5.5
5.0
ns
t
w
(H)
Latch Enable pulse width,
High
Waveform 1
4.5
5.0
ns
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