參數(shù)資料
型號(hào): 74F670
廠商: NXP Semiconductors N.V.
英文描述: 4 x 4 register file 3-State
中文描述: 4 × 4寄存器三態(tài)
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 97K
代理商: 74F670
Philips Semiconductors
Product specification
74F670
4 x 4 register file (3-State)
2
1990 Jul 12
853-0014 99965
FEATURES
Simultaneous and Independent Read and Write operations
Expandable to almost any word size and bit length
3-State outputs
DESCRIPTION
The 74F670 is a 16-bit 3-State Register File organized as 4 words of
4 bits each. Separate Read and Write Address and Enable inputs
are available, permitting simultaneous writing into one word location
and reading from another location. The 4-bit word to be stored is
presented to four data inputs.
The Write address inputs (WA and WB) determine the location of the
stored word. The Write Address inputs should only be changed
when the Write Enable input (WE) is High for conventional
operation. When the WE is Low, the data is entered into the
addressed location.
The addressed location remains transparent to the data while the
WE is Low. Data supplied at the inputs will be read out in true
(non-inverting) form from the 3-State outputs. Data and address
inputs are inhibited when the WE is High. Direct acquisition of data
stored in any of the four registers is made possible by individual
Read Address inputs (RA, RB). The addressed word appears at the
four outputs when the Read Enable (RE) is Low. Data outputs are in
the high impedance “off” state when the RE is High. This permits
outputs to be tied together to increase the word capacity to very
large numbers.
Up to 128 devices can be stacked to increase the word size to 512
locations by tying the 3-State outputs together. Since the limiting
factor for expansion is the output High current, further stacking is
possible by tying pullup reisistors to the outputs to increase the I
OH
current available. Design of the Read Enable signals for the stacked
devices must ensure that there is no overlap in the Low levels which
cause more than one output to be active at the same time. Parallel
expansion to generate n-bit words is accomplished by driving the
Enable and address inputs of each device in parallel.
PIN CONFIGURATION
7
14
13
12
11
10
9
6
5
4
3
2
1
V
CC
D0
WE
RE
Q1
RA
D2
Q3
D1
GND
D3
RB
SF01178
Q0
WB
Q2
WA
8
16
15
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F670
6.5ns
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG DWG #
16-pin plastic DIP
N74F670N
SOT38-4
16-pin plastic SOL
N74F670D
SOT162-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
D0 - D3
Data inputs
1.0/1.0
WA, WB
Write address inputs
1.0/1.0
RA, RB
Read address inputs
1.0/1.0
WE
Write Enable inputs
1.0/1.0
20mA/0.6mA
RE
Read Enable inputs
1.0/1.0
20mA/0.6mA
Q0–Q3
Data output
150/40
3.0mA/24mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
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