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參數(shù)資料
| 型號： | 74F595 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit shift register with output laches 3-State |
| 中文描述： | 8位的移位寄存器輸出懈怠三態(tài) |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 74F595 |
Philips Semiconductors
Product specification
74F595
8-bit shift register with output latches (3-State)
1990 Apr 18
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NO TAG
MIN
TYP
NO TAG
MAX
UNIT
Qs
= 1mA
I
OH
=–1mA
±
10%V
CC
2.5
V
V
OH
High level output voltage
High-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
=MIN
±
5%V
CC
2.7
3.4
V
Q0 Q7
Q0–Q7
= 3mA
I
OH
=–3mA
±
10%V
CC
2.4
V
±
5%V
CC
2.7
3.3
V
Qs
I
OL
= 20mA
±
10%V
CC
0.30
0.50
V
V
OL
Low level output voltage
Low-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN,
±
5%V
CC
0.30
0.50
V
Q0 Q7
Q0–Q7
I
OL
= 24mA
±
10%V
CC
0.35
0.50
V
±
5%V
CC
0.35
0.50
V
V
IK
I
I
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
μ
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
–20
mA
I
OZH
Off-state output current,
High level of voltage applied
Q0–Q7
only
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off-state output current,
Low level of voltage applied
Q0–Q7
only
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
Short-circuit output current
NO TAG
V
CC
= MAX
–60
–150
mA
I
CCH
55
80
mA
I
CC
Supply current (total)
I
CCL
V
CC
= MAX
70
100
mA
I
CCZ
65
95
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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