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參數(shù)資料
| 型號： | 74F595 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit shift register with output laches 3-State |
| 中文描述： | 8位的移位寄存器輸出懈怠三態(tài) |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 99K |
| 代理商： | 74F595 |
Philips Semiconductors
Product specification
74F595
8-bit shift register with output latches (3-State)
1990 Apr 18
3
LOGIC SYMBOL
12
13
OE
STCP
15
1
2
3
Q0
Q1
Q2
Q3
10
11
SHCP
SHR
SF01097
V
= Pin 16
GND = Pin 8
14
Ds
9
Qs
4
5
6
Q4
Q5
Q6
7
Q7
IEC/IEEE SYMBOL (IEEE/IEC)
SF01098
14
1D
EN3
C1/
13
12
10
11
2
3
4
C2
3
15
1
R
SRG8
2D
6
7
9
5
3
2D
MODE SELECT – FUNCTION TABLE
INPUTS
INTERNAL SHIFT
REGISTERS
INTERNAL STORAGE
REGISTER
OUTPUTS
OPERATING
MODES
OE
SHR
SHCP
STCP
Dn
O0
O1–O7
Q0–Q7
Q0–Q7
QS
H
H
↑
↑
X
O0
O1–O7
Q0–Q7
Z
Q7
No Change
H
L
X
↑
X
L0
L
Q0–Q7
Z
L
Clear shift
register, hold latch
L
L
X
↑
X
L0
L
Q0–Q7
Q0–Q7
L
H
H
↑
↑
ds
Ds
o0–o6
Q0–Q7
Z
o6
Shift
L
H
↑
↑
ds
Ds
o0–o6
Q0–Q7
Q0–Q7
o6
H
H
↑
↑
X
O0
O1–O7
o0–o7
Z
Q7
Store
L
H
↑
↑
X
O0
O1–O7
o0–o7
o0–o7
Q7
H
H
↑
↑
ds
Ds
o0–o6
o0–o7*
Z
o6
Store then Shift
Store, then Shift
L
H
↑
↑
ds
Ds
o0–o6
o0–o7*
o0–o*
o6
H =
L
X =
Z =
dn (on)=Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition
↑
=
Low-to-High clock transition
↑
=
Not a Low-to-High clock transition
*
=
When clocking both SHCP and STCP simultaneously the Shift Register state will always be one clock pulse ahead of the Storage
Register
High voltage level
Low voltage level
Don’t care
High impedance
=
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