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參數(shù)資料
| 型號(hào)： | 74F5074 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual D-type flip-flop/clock driver(同步雙D觸發(fā)器/時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 同步雙D型flip-flop/clock驅(qū)動(dòng)程序（同步雙?觸發(fā)器/時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 74F5074 |
Philips Semiconductors
Product specification
74F5074
Synchronizing dual D-type flip-flop/clock driver
September 14, 1990
5
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
7
8
9
10
10
12
10
11
10
10
10
9
10
8
10
7
10
6
10
14
10
15
= f
C
f
I
t’ in nanoseconds
MTBF in seconds
one year
10
6
10
8
10
10
10
12
one week
10,000 years
100 years
SF00589
NOTE:
V
CC
= 5V, T
amb
= 25
°
C,
τ
=135ps, To = 9.8 X 10
6
sec
Figure 4.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
°
C
V
CC
τ
T
0
5.5V
125ps
1.0 X 10
9
sec
1.3 X 10
10
sec
3.4 X 10
13
sec
T
amb
= 25
°
C
T
amb
= 70
°
C
τ
T
0
τ
T
0
138ps
5.4 X 10
6
sec
9.8 X 10
6
sec
5.1 X 10
8
sec
160ps
1.7 X 10
5
sec
3.9 X 10
4
sec
7.3 X 10
4
sec
5.0V
115ps
135ps
167ps
4.5V
115ps
132ps
175ps
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
Q
MODE
L
H
X
X
H
L
Asynchronous set
H
L
X
X
L
H
Asynchronous reset
L
L
X
X
H
H
Undetermined*
H
H
↑
↑
↑
h
H
L
Load “1”
H
H
l
L
H
Load “0”
H
H
X
NC
NC
Hold
NOTES:
H =
h
=
L
=
l
=
NC=
X =
↑
=
↑
=
*
=
High voltage level
High voltage level one setup time prior to low–to–high clock transition
Low voltage level
Low voltage level one setup time prior to low–to–high clock transition
No change from the previous setup
Don’t care
Low–to–high clock transition
Not low–to–high clock transition
This setup is unstable and will change when either set or reset return to the high level
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