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參數(shù)資料
| 型號： | 74F256 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual addressable latch |
| 中文描述： | 雙尋址閉鎖 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 104K |
| 代理商： | 74F256 |
Philips Semiconductors
Product specification
74F256
Dual addressable latch
1988 Nov 29
6
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
V
CC
= +5V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5V
±
10%
C
L
= 50pF, R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation delay
Dn to Qn
Waveform 2
4.0
3.0
7.0
5.0
9.5
7.0
4.0
2.5
10.0
7.5
ns
Propagation delay
E to Qn
Waveform 1
4.5
3.0
8.0
5.0
10.5
7.0
4.5
3.0
12.0
7.5
ns
Propagation delay
An to Qn
Waveform 3
5.0
4.5
10.0
8.5
14.0
9.5
5.0
4.0
14.5
10.0
ns
t
PHL
Propagation delay
MR to Qn
Waveform 4
5.0
7.0
9.0
4.5
10.0
ns
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(L)
t
w
(L)
Setup time, High or Low
Dn to E
Waveform 5
3.0
6.5
3.0
7.0
ns
Hold time, High or Low
Dn to E
Waveform 5
0
0
0
0
ns
Setup time, High or Low
An to E
1
Waveform 6
2.0
2.0
2.0
2.0
ns
Hold time, High or Low
An to E
2
Waveform 6
0
0
0
0
ns
E Pulse width, Low
Waveform 1
7.5
8.0
ns
MR Pulse width, Low
Waveform 4
3.0
3.0
ns
NOTES:
1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
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