
Philips Semiconductors
Product specification
74F225
16
×
5 asynchronous FIFO (3-State)
2
June 15, 1992
853-1652 06992
FEATURES
Independent synchronous inputs and outputs
Organized as 16 words of 5 bits
DC to 25MHz data rate
3–State outputs
Cascadable in word–width and depth direction
DESCRIPTION
This 80–bit active element First–In–First–Out (FIFO) is a monolithic
Schottky–clamped transistor–transistor logic (STTL) array organized
as 16–words of 5–bits each. A memory system using the ’F225 can
be easily expanded in multiples of 16–words of 5–bits as shown in
Figure 1. The 3–State outputs controlled by a single enable input
(OE) make bus connection and multiplexing simple. The ’F225
processes data in a parallel format at any desired clock rate from
DC to 25MHz. Status of the ’F225 is provided by three outputs, Input
Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready
(OR). The data outputs are non–inverting with respect to the data
inputs and are disabled when the OE input is High. When OE is
Low, the data outputs are enabled to function as totem–pole outputs.
TYPE
TYPICAL f
MAX
TYPICAL SUPPLY
CURRENT
( TOTAL)
74F225
25MHz
65mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F225N
PKG DWG #
20–pin plastic DIP
SOT146-1
20–pin plastic SOL
N74F225D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
CPA, CPB
Load clock A and load clock B inputs
1.0/0.033
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
D0 – D4
Data inputs
1.0/0.033
OE
Output enable input (active–Low)
1.0/0.033
UNCPIN
Unload clock input
1.0/0.033
MR
Master reset input (active–Low)
1.0/0.033
IR
Input ready output
50/33
1.0mA/20mA
UNCPOUT
Unload clock output (active–Low)
50/33
1.0mA/20mA
Q0 – Q4
Data outputs
150/40
3.0mA/24mA
OR
Output ready output
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
RESET MODE
A High–to–Low transition on the Master Reset (MR) input invalidates
all data stored in the FIFO by clearing the control logic and setting
OR Low. This High–to–Low transition on the MR input does not
effect the data outputs but since OR is driven Low, it signifies invalid
data on the outputs.
WRITE MODE
Data may be written into the array on the Low–to–High transition of
either load clock (CPA or CPB) input. When writing data into the
FIFO, one of the load clock inputs must be held High while the other
strobes data into the FIFO. This arrangement allows either load
clock to function as an inhibit for the other. Input Ready (IR)
monitors the status of the last word location and signifies when the
FIFO is full. This output is High whenever the FIFO is available to
accept new data. The unload clock output (UNCPOUT) also
monitors the last word location. This output generates a
Low–logic–level pulse (synchronized to the internal clock pulse)
when the last word location is vacant
READ MODE
The Output Ready (OR) output is High when valid data is present on
the data outputs. Data in the array is shifted on the Low–to–High
transition of the Unload Clock Input (UNCPIN). In order for Output
Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be
High.