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參數(shù)資料
| 型號(hào)： | 74F193 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Up/down binary counter with separate up/down clocks(帶分離加減時(shí)鐘的加減二進(jìn)制計(jì)數(shù)器) |
| 中文描述： | 向上/向下二進(jìn)制計(jì)數(shù)器分別向上/向下鐘表（帶分離加減時(shí)鐘的加減二進(jìn)制計(jì)數(shù)器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 104K |
| 代理商： | 74F193 |
Philips Semiconductors
Product specification
74F193
Up/down binary counter with separate up/down clocks
2
1995 Jul 17
853-0353 15459
FEATURES
Synchronous reversible 4-bit counting
Asynchronous parallel load capability
Asynchronous reset (clear)
Cascadable without external logic
DESCRIPTION
The 74F193 is a 4-bit synchronous up/down counter in the binary
mode. Separate up/down clocks, CP
U
and CP
D
respectively,
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CP
U
clock is
pulsed while CP
D
is held High, the device will count up. If CP
D
clock
is pulsed while CP
U
is held High, the device will count down. The
device can be cleared at any time by the asynchronous reset pin. It
may also be loaded in parallel by activating the asynchronous
parallel load pin.
Inside the device are four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count
down functions.
Each flip-flop contains JK feedback from slave to master, such that a
Low-to-High transition on the CP
D
input will decrease the count by
one, while a similar transition on the CP
U
input will advance the
count by one.
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as
either clock input is Low. Applications requiring reversible operation
must make the reversing decision while the activating clock is High
to avoid erroneous counts.
The Terminal Count Up (TC
U
) and Terminal Count Down (TC
D
)
outputs are normally High. When the circuit has reached the
maximum count state of 15, the next High-to-Low transition of CP
U
will cause TC
U
to go Low. TC
U
will stay Low until CP
U
goes High
again, duplicating the count up clock, although delayed by two gate
delays. Likewise, the TC
D
output will go Low when the circuit is in
the zero state and the CP
D
goes Low. The TC outputs can be used
as the clock input signals to the next higher order circuit in a
multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous since there is a
two-gate delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
during and after a reset or load operation, the next Low-to-High
transition of the clock will be interpreted as a legitimate signal and
will be counted.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F193
125MHz
32mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F193N
PKG DWG #
16-pin plastic DIP
SOT38-4
16-pin plastic SO
N74F193D
SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D1
Q1
Q0
CP
D
CP
U
Q2
Q3
D0
TC
D
TC
U
D2
D3
PL
GND
MR
V
CC
SF00745
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20
μ
A/0.6mA
20
μ
A/1.8mA
20
μ
A/1.8mA
20
μ
A/0.6mA
20
μ
A/0.6mA
D0 - D3
Data inputs
1.0/1.0
CP
U
CP
D
PL
Count up clock input (active rising edge)
1.0/3.0
Count down clock input (active rising edge)
1.0/3.0
Asynchronous parallel load control input (active Low)
1.0/1.0
MR
Asynchronous master reset input
1.0/1.0
Q0 - Q3
Flip-flop outputs
50/33
1.0mA/20mA
TC
U
TC
D
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
Terminal count up (carry) output (active Low)
50/33
1.0mA/20mA
Terminal count down (borrow) output (active Low)
50/33
1.0mA/20mA
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| 74F195A | 4-bit parallel-access shift register(4位并行訪問移位寄存器) |
| 74F198 | 8-bit bidirectional universal shift register(8位雙向通用移位寄存器) |
| 74F199 | 8-bit parallel-access shift register |
| 74F20DC | Dual 4-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F193D | 制造商:Yageo / Phycomp 功能描述:Counter Single 4-Bit Async Binary UP/Down 16-Pin SO Tube |
| 74F193DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up/Down Counter |
| 74F193N | 制造商:Yageo / Phycomp 功能描述: |
| 74F193PC | 功能描述:計(jì)數(shù)器移位寄存器 Up/Down Binary Ctr RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74F193PC | 制造商:Fairchild Semiconductor Corporation 功能描述:74F FAST TTL 74F193 DIP16 5.5V |
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