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參數(shù)資料
| 型號(hào)： | 74F189SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64-Bit Random Access Memory with 3-STATE Outputs |
| 中文描述： | 16 X 4 STANDARD SRAM, 27 ns, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74F189SJ |
Philips Semiconductors
Product specification
74F189A
64-bit TTL bipolar RAM, inverting (3-State)
1990 Feb 23
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
PLH
t
PHL
Access time
Propagation delay
An to Qn
Waveform 1
2.5
2.0
5.0
4.5
8.0
8.0
2.5
2.0
8.0
8.0
ns
t
PZH
t
PZL
t
PHZ
t
PLZ
Enable time
CE to Qn
Waveform 2
2.0
2.0
3.5
4.0
6.0
7.0
1.5
2.0
7.0
7.5
ns
Disable time
CE to Qn
Waveform 3
2.5
1.5
4.5
3.0
7.0
5.5
2.0
1.5
8.0
6.0
ns
t
PZH
t
PZL
t
PHZ
t
PLZ
Write recovery time
Enable time
WE to Qn
Waveform 4
2.0
2.5
4.0
4.5
6.5
7.5
2.0
2.5
7.0
8.0
ns
Disable time
WE to Qn
Waveform 4
3.5
1.5
5.5
3.5
8.5
6.5
3.0
1.5
9.0
7.0
ns
AC SETUP REQUIREMENT
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
Setup time, high or low
An to WE
Waveform 4
4.5
4.5
5.0
5.0
ns
Hold time, high or low
An to WE
Waveform 4
0
0
0
0
ns
Setup time, high or low
Dn to WE
Waveform 4
7.5
6.5
9.0
8.0
ns
Hold time, high or low
Dn to WE
Waveform 4
0
0
0
0
ns
t
su
(L)
Setup time, low
CE (falling edge) to WE (falling edge)
Waveform 4
0
0
ns
t
h
(L)
Hold time, low
WE (falling edge) to WE (rising edge)
Waveform 4
6.5
7.5
ns
t
w
(L)
Pulse width, low
WE
Waveform 4
7.0
8.0
ns
AC WAVEFORMS FOR READ CYCLES
V
M
V
M
Qn
An
t
PHL
t
PLH
NOTE:
For all waveforms, V
M
= 1.5V.
SF00303
Waveform 1. Read cycle, address access time
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