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參數(shù)資料
| 型號： | 74F189SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64-Bit Random Access Memory with 3-STATE Outputs |
| 中文描述： | 16 X 4 STANDARD SRAM, 27 ns, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74F189SJ |
Philips Semiconductors
Product specification
74F189A
64-bit TTL bipolar RAM, inverting (3-State)
1990 Feb 23
4
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
T
A
= –40 to +85
°
C
V
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
Supply voltage
4.5
5.0
5.5
High–level input voltage
2.0
V
Low–level input voltage
0.8
V
Input clamp current
–18
mA
High–level output current
–3
mA
Low–level output current
24
mA
°
C
T
amb
Operating free air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.4
V
V
IH
= MIN, I
OH
= MAX
2.7
3.4
V
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX
0.35
0.50
V
V
IH
= MIN, I
OL
= MAX
0.35
0.50
V
V
IK
I
I
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
-0.73
-1.2
V
Input current at maximum input voltage
100
μ
A
μ
A
I
IH
I
IL
High–level input current
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
20
Low–level input current
others
-0.6
mA
CE, WE
-1.2
mA
I
OZH
Offset output current,
high–level voltage applied
V
CC
= MAX, V
I
= 2.7V
50
μ
A
I
OZL
Offset output current,
low–level voltage applied
Short-circuit output current
3
V
CC
= MAX, V
I
= 0.5V
–50
μ
A
I
OS
I
CC
C
IN
C
OUT
V
CC
= MAX
V
CC
= MAX, CE = WE = GND
V
CC
= 5V, V
IN
= 2.0V
V
CC
= 5V, V
OUT
= 2.0V
-60
-150
mA
Supply current (total)
55
80
mA
Input capacitance
4
pF
Output capacitance
7
pF
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
= 5V, T
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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