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參數(shù)資料
| 型號： | 74F1763 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Intelligent DRAM controller IDC |
| 中文描述： | IDC的智能內(nèi)存控制器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 117K |
| 代理商： | 74F1763 |
Philips Semiconductors
Product specification
74F1763
Intelligent DRAM controller (IDC)
2
1999 Jan 08
853–1406 20619
FEATURES
DRAM signal timing generator
Automatic refresh circuitry
Selectable row address hold and RAS precharge times
Facilitates page mode accesses
Controls 1 MBit DRAMs
Intelligent burst-mode refresh after page-mode access cycles
PRODUCT DESCRIPTION
The Philips Semiconductors Intelligent Dynamic RAM Controller is a
1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM
Controller. It contains automatic signal timing, address multiplexing
and refresh control required for interfacing with dynamic RAMs.
Additional features have been added to this device to take
advantage of technological advances in Dynamic RAMs. A
Page-Mode access pin allows the user to assert RAS for the entire
access cycle rather than the pre-defined four-clock-cycle pulse width
used for normal random access cycles. In addition, the user has the
ability to select the RAS precharge time and Row-Address Hold time
to fit the particular DRAMs being used. DTACK has been modified
from previous family parts to become a negative true, tri-stated
output. The options for latched or unlatched address are contained
on a single device by the addition of an Address Latch Enable (ALE)
input. Finally, a burst refresh monitor has been added to ensure
complete refreshing after length page-mode access cycles. With a
maximum clock frequency of 100 MHz, the F1763 is capable of
controlling DRAM arrays with access times down to 40 nsec.
TYPE
f
MAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F1763
100 MHz
150 mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
V
CC
= 5V
T
A
= 0 C TO 70 C
N74F1763N
10%;
PKG DWG #
48-pin Plastic DIP
SOT240-1
INPUT AND OUTPUT LOADING FAN-OUT TABLE
NO TAG
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
REQ
DRAM Request Input
1.0/1.0
20 A/0.6 mA
CP
Clock Input
1.0/1.0
20 A/0.6 mA
PAGE
Page Mode Select Input
1.0/1.0
20 A/0.6 mA
PRECHRG
RAS Precharge Select Input
1.0/1.0
20 A/0.6 mA
HLDROW
Row Hold Select Input
1.0/1.0
20 A/0.6 mA
DTACK
Data Transfer Ack. Output
50/80
35 mA/60 mA
GNT
Access Grant Output
50/80
35 mA/60 mA
RCP
Refresh Clock Input
1.0/1.0
20 A/0.6 mA
RA0–9
Row Address Inputs
1.0/1.0
20 A/0.6 mA
CA0–9
Column Address Inputs
1.0/1.0
20 A/0.6 mA
ALE
Address Latch Enable Input
1.0/1.0
20 A/0.6 mA
RAS
Row Address Strobe Output
NA
35 mA/60 mA
CAS
Column Address Strobe Output
NA
35 mA/60 mA
MA0–9
DRAM Address Outputs
NA
35 mA/60 mA
NOTES:
One (1.0) FAST Unit Load is defined as 20 A in the HIGH state and 0.6 mA in the LOW state.
FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details.
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