參數(shù)資料
型號: 74F132
廠商: NXP Semiconductors N.V.
英文描述: Quad 2-input NAND Schmitt trigger(四2輸入與非門施密特觸發(fā)器)
中文描述: 四2輸入與非施密特觸發(fā)器(四2輸入與非門施密特觸發(fā)器)
文件頁數(shù): 4/8頁
文件大?。?/td> 71K
代理商: 74F132
Philips Semiconductors
Product specification
74F132
Quad 2-input NAND Schmitt trigger
1991 Jun 26
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
T+
V
T–
V
T
Positive-going threshold
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= MIN,
V
I=
V
T–MAX
, I
OH
= MAX
V
CC
= MIN,
V
I=
V
T+MAX
, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= 5.0V, V
I
=V
T+
V
CC
= 5.0V, V
I
=V
T–
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
1.5
1.7
2.0
V
Negative-going threshold–
0.7
0.9
1.1
V
Hysteresis (V
T+
V
T–
)
0.4
0.8
V
V
OH
High level output voltage
High-level output voltage
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
2.7
3.4
V
OL
Low level output voltage
Low-level output voltage
0.30
0.50
V
0.30
0.50
V
IK
I
T+
I
T–
I
I
I
IH
I
IL
I
OS
Input clamp voltage
–0.73
–1.2
V
Input current at positive-going threshold
0
μ
A
μ
A
μ
A
Input current at negative-going threshold
–350
Input current at maximum input voltage
100
High-level input current
20
μ
A
Low-level input current
Short-circuit output current
3
–0.6
mA
–60
–150
mA
I
CC
Supply current (total)
I
CCH
I
CCL
V
CC
= MAX
V
I N
= GND
V
IN
= 4.5V
8.5
12.0
mA
13.0
19.5
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
= 5V, T
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
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