- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360419 > 74AVC16836DGG (NXP SEMICONDUCTORS) 20-bit registered driver with inverted register enable 3-State PDF資料下載
參數(shù)資料
| 型號： | 74AVC16836DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20-bit registered driver with inverted register enable 3-State |
| 中文描述： | AVC SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 90K |
| 代理商： | 74AVC16836DGG |
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Preliminary specification
74AVC16836
1999 Jul 23
6
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
≤
2.0 ns; C
L
= 30 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3
±
0.3 V
TYP
1
V
CC
= 2.5
±
0.2 V
TYP
1
V
CC
= 1.8
±
0.15 V
TYP
1
V
CC
= 1.2 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
TYP
Propagation delay
An to Yn
1, 7
0.7
1.7
2.5
0.8
2.0
3.0
1.0
2.6
4.5
5.2
t
PHL
/t
PLH
Propagation delay
LE to Yn
2, 7
0.7
2.0
3.0
0.8
2.4
3.6
1.0
3.0
5.5
6.0
ns
Propagation delay
CP to Yn
3, 7
0.7
1.9
2.9
0.8
2.2
3.3
0.9
2.8
5.2
5.5
t
PZH
/t
PZL
3-State output enable
time OE to Yn
6, 7
1.0
2.5
4.5
1.0
2.8
5.0
1.5
3.5
6.5
6.0
ns
t
PHZ
/t
PLZ
3-State output disable
time OE to Yn
6, 7
1.0
2.5
4.0
1.0
2.4
4.5
1.5
4.0
6.5
6.0
t
W
CP pulse width HIGH
or LOW
3, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
ns
LE pulse width HIGH
2, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
t
SU
Set-up time An to CP
5, 7
0.3
–
–
0.4
–
–
0.5
–
–
–
ns
Set-up time An to LE
4, 7
0.3
–
–
0.4
–
–
0.5
–
–
–
t
h
Hold time An to CP
5, 7
0.3
–
–
0.4
–
–
0.5
–
–
ns
Hold time An to LE
4, 7
0.3
–
–
0.4
–
–
0.5
–
–
F
max
Maximum clock pulse
frequency
3, 7
500
–
–
400
–
–
250
–
–
MHz
NOTES:
1. All typical values are measured at T
amb
= 25
°
C and at V
CC
= 1.8 V, 2.5 V, 3.3 V.
AC WAVEFORMS FOR V
CC
= 3.0 V TO 3.6 V RANGE
V
M
= 0.5 V
V
X
= V
OL
+ 0.300 V
V
Y
= V
OH
– 0.300 V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
AC WAVEFORMS FOR V
CC
= 2.3 V TO 2.7 V AND
V
CC
< 2.3 V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.15 V
V
Y
= V
– 0.15 V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
A
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Y
OUTPUT
SH00132
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
V
M
V
M
V
M
SH00165
NOTE: V
M
= 0.5 V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
相關PDF資料 |
PDF描述 |
|---|---|
| 74AVCH16244 | 16-bit buffer/line driver; 3.6 V tolerant; 3-state |
| 74AVCH16245 | 16-bit transceiver with direction pin;3.6 V tolerant; 3-state(3.6 V 容限,三態(tài),帶定向引腳的16位收發(fā)器) |
| 74AVCM162834 | 18-bit registered driver with inverted register enable with 15Ω termination resistors (3-State)(帶15Ω終端電阻的具有反相寄存使能的18位寄存驅(qū)動器（三態(tài)）) |
| 74AVCM162835 | 18-bit registered driver with 15Ω termination resistors (3-State)(帶15Ω終端電阻的18位寄存驅(qū)動器（三態(tài)）) |
| 74AVCM162836 | 20-bit registered driver with inverted register enable and 15 ohm termination resistors 3-State |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74AVC16T245 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit dual supply translating transceiver with configurable voltage translation; 3-state |
| 74AVC16T245BQ,518 | 功能描述:總線收發(fā)器 16-BIT DUAL-SUP XCVR W/CONFIG VOLT 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74AVC16T245BX | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit dual supply translating transceiver with configurable voltage translation; 3-state |
| 74AVC16T245BX,518 | 功能描述:轉(zhuǎn)換 - 電壓電平 6ns 1.6V 1W RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74AVC16T245BX518 | 制造商:NXP Semiconductors 功能描述:IC 16BIT TXRX TRI-ST HXQFN |
發(fā)布緊急采購，3分鐘左右您將得到回復。