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參數資料
| 型號： | 74AVC16836DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20-bit registered driver with inverted register enable 3-State |
| 中文描述： | AVC SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁數： | 3/10頁 |
| 文件大小： | 90K |
| 代理商： | 74AVC16836DGG |
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Preliminary specification
74AVC16836
1999 Jul 23
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
28
NC
No connection
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
20, 21, 23, 24, 26, 27
Y
0
to Y
19
Data outputs
4, 11, 18, 25, 32, 35, 39,
46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
1
OE
Output enable input
(active LOW)
29
LE
Latch enable input
(active LOW)
56
CP
Clock input
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
31, 30
A
0
to A
19
Data inputs
LOGIC SYMBOL
CP
LE
D
OE
CP
LE
A
0
Y
0
TO THE 19 OTHER CHANNELS
SH00163
LOGIC SYMBOL (IEEE/IEC)
1
1
56
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
55
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
3D
1
2C3
EN1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
OE
CP
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
14
Y
15
Y
16
Y
17
LE
C3
G2
SH00160
A
18
A
19
Y
18
Y
19
26
27
31
30
FUNCTION TABLE
INPUTS
OUTPUTS
OE
H
LE
X
CP
X
A
X
Z
L
L
X
L
L
L
L
X
↑
↑
H
H
H
L
H
L
L
L
H
H
H
L
H
X
Y
01
Y
02
L
=
=
=
=
=
H
L
X
H
L
X
Z
↑
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
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