參數(shù)資料
型號(hào)： 74AVC16835DGG
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 18-bit registered driver 3-State
中文描述： AVC SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝： PLASTIC, TSSOP-56
文件頁(yè)數(shù)： 2/10頁(yè)
文件大小： 89K
代理商： 74AVC16835DGG
Philips Semiconductors
Preliminary specification
74AVC16835
18-bit Registered Driver (3-State)
2
1999 Jul 23
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Power off disables 74AVC16835 outputs, permitting Live Insertion
DESCRIPTION
The 74AVC16835 is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
NC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
GND
V
CC
GND
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
SH00130
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.0 ns; C
L
= 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
2.6
2.0
1.7
2.8
2.2
1.8
5.0
25
6
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
ns
t
PHL
/t
PLH
Propagation delay
LE to Yn;
CP to Yn
Input capacitance
ns
C
I
pF
C
PD
Power dissipation capacitance per buffer
Power dissi ation ca acitance er buffer
V
I
= GND to V
CC1
Outputs enabled
Output disabled
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
ORDER CODE
DRAWING
NUMBER
SOT364-1
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
74AVC16835 DGG
相關(guān)PDF資料
PDF描述
74AVC16836A 20-bit registered driver with inverted register enable and Dynamic Controlled OutputsE (3-State)(具有動(dòng)態(tài)控制輸出和反相寄存使能的20位寄存驅(qū)動(dòng)器（三態(tài)）)
74AVC16836 20-bit registered driver with inverted register enable 3-State
74AVC16836DGG 20-bit registered driver with inverted register enable 3-State
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參數(shù)描述
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74AVC16835DGGRG4 功能描述:通用總線函數(shù) 18B Univ Bus Driver RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74AVC16835DGVRE4 功能描述:通用總線函數(shù) 18B Univ Bus Driver RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74AVC16835DGVRG4 功能描述:通用總線函數(shù) 18B Univ Bus Driver RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74AVC16836 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit registered driver with inverted register enable 3-State
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