- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360417 > 74ALVT16260 (NXP Semiconductors N.V.) 12-bit to 24-bit multiplexed D-type latches(3-State)(12位至 24位多路D鎖存器(三態(tài)）) PDF資料下載
參數(shù)資料
| 型號： | 74ALVT16260 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 12-bit to 24-bit multiplexed D-type latches(3-State)(12位至 24位多路D鎖存器(三態(tài)）) |
| 中文描述： | 12位至24位復(fù)用D型鎖存器（3態(tài)）（12位至24位多路?鎖存器（三態(tài)）） |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 91K |
| 代理商： | 74ALVT16260 |
Philips Semiconductors
Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
2
1998 Jan 30
853-2046-18918
FEATURES
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
Distributed V
CC
and GND pin configuration minimizes high-speed
switching noise.
Output capability (–32mA I
OH
, 64mA I
OL
).
Bus hold inputs eliminate the need for external pull-up resistors.
5V I/O compatible
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
CC
through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
2.5V
3.3V
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
Propagation delay
C = 50 pF
3.5
2.8
ns
nAx to nBx nBx to nAx
3.3
2.6
Input capacitance
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
Outputs disabled
4
4
pF
Output capacitance
9
9
pF
Total supply current
100
80
μ
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74ALVT16260 DL
AV16260 DL
SOT371-1
56-Pin Plastic TSSOP Type II
74ALVT16260 DGG
AV16260 DGG
SOT364-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVT162731DGG | LCA4/0-14 BENT 45 DEG- RoHS Compliant: Yes |
| 74ALVT162731DL | 2.5V/3.3V 1-to-4 address register/driver with 30ohm termination resistors 3-State |
| 74ALVT162731 | 2.5V/3.3V 1-to-4 address register/ driver with 30Ω termination resistors (3-State)(帶30 Ω終端電阻器的2.5V/3.3V 1至4地址寄存器/驅(qū)動器 (三態(tài)）) |
| 74ALVT162821 | 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30Ω termination resistors(3-State)(帶30 Ω終端電阻器2.5V/3.3V 20位總線接口上升沿觸發(fā)D觸發(fā)器（三態(tài)）) |
| 74ALVT162823 | 18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)(帶30 Ω終端電阻器的具有復(fù)位和使能的18位總線接口D觸發(fā)器（三態(tài)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVT16260DG | 功能描述:閉鎖 12-BIT TO 24-BIT MULITPLEXED D RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVT16260DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:12-bit to 24-bit multiplexed D-type latches 3-State |
| 74ALVT16260DGG,112 | 功能描述:閉鎖 12-BIT TO 24-BIT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVT16260DGG,118 | 功能描述:閉鎖 12-BIT TO 24-BIT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVT16260DG-T | 功能描述:閉鎖 12-BIT TO 24-BIT MULITPLEXED D RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。