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參數(shù)資料
| 型號： | 74ALVCH16825 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Automotive Catalog Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 125 |
| 中文描述： | 18位緩沖器/驅(qū)動器三態(tài) |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 73K |
| 代理商： | 74ALVCH16825 |
Philips Semiconductors
Product specification
74ALVCH16825
18-bit buffer/driver (3-State)
2
1998 Jul 27
853-2097 19785
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with
3-State outputs for bus-oriented applications.
The 74ALVCH16825 consists of two 9-bit sections with separate
output enable signals. For either 9-bit buffer section, the two output
enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
LOW for corresponding D outputs to be active. If either output
enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.
The 74ALVCH16825 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE1
1Y
1
1Y
1
1Y
2
1Y
3
1Y
4
1Y
5
1Y
6
GND
V
CC
GND
1Y
7
1Y
8
GND
GND
2Y
0
2Y
1
GND
2Y
2
2Y
3
2Y
4
V
CC
2Y
5
2Y
6
GND
2Y
7
2OE1
1A
0
1A
1
GND
1A
2
1A
3
V
CC
1A
4
1A
5
1A
6
GND
1A
7
1A
8
GND
GND
2A
0
2A
1
GND
2A
2
2A
3
2A
4
V
CC
2A
5
2A
6
GND
2A
7
2A
8
2Y
8
2OE2
1OE2
SH00139
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5ns
SYMBOL
Propagation delay
CP to Qn
C
I
Input capacitance
PARAMETER
CONDITIONS
TYPICAL
2.0
2.0
4.0
19
3
UNIT
t
PHL
/t
PLH
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
ns
pF
C
PD
Power dissipation capacitance per latch
Power dissi ation ca acitance er latch
V
I
= GND to V
CC1
Output enabled
Output disabled
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
OUTSIDE NORTH
AMERICA
74ALVCH16825 DGG
NORTH AMERICA
DRAWING
NUMBER
SOT364-1
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
ACH16825 DGG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVCH16827 | 20-bit buffer/line driver, non-inverting 3-State |
| 74ALVCH16841DL | 20-bit bus interface D-type latch (3-State) |
| 74ALVCH16841 | 20-bit bus interface D-type latch 3-State |
| 74ALVCH16843 | 3-Line To 8-Line Decoders/Demultiplexers 16-SSOP -40 to 85 |
| 74ALVCH16952 | 16-bit registered transceiver 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVCH16825DG | 功能描述:緩沖器和線路驅(qū)動器 16BIT BUS INTER. 3ST RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ALVCH16825DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit buffer/driver 3-State |
| 74ALVCH16825DGG,11 | 功能描述:緩沖器和線路驅(qū)動器 16BIT BUS INTER. 3ST RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ALVCH16825DGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVCH16825DGG,118 | 制造商:NXP Semiconductors 功能描述: |
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