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參數(shù)資料
| 型號(hào)： | 74ALVCH162601 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 18-bit universal bus transceiver with 30Ω termination resistor (3-State)(帶30Ω終端電阻器的18位通用總線收發(fā)器（三態(tài)）) |
| 中文描述： | 18 -30Ω端接電阻位通用總線收發(fā)器（3態(tài)）（帶30Ω終端電阻器的18位通用總線收發(fā)器（三態(tài)）） |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大?。?/td> | 90K |
| 代理商： | 74ALVCH162601 |
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1999 Oct 14
2
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30
termination resistor; 3-state
74ALVCH162601
FEATURES
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
flow-through
standard pin-out architecture
Low inductance multiple V
CC
and
ground pins for minimum noise and
ground bounce
All data inputs have bus hold
circuitry
Integrated 30
termination
resistors.
DESCRIPTION
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OE
AB
and OE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates in the
transparent mode when LE
AB
is HIGH. When LE
AB
is LOW, the A data is
latched if CP
AB
is held at a HIGH or LOW logic level. If LE
AB
is LOW, the A-bus
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CP
AB
.
When OE
AB
is LOW, the outputs are active. When OE
AB
is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CE
BA
/CE
AB
).
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
.
To ensure the high-impedance state during power-down, OE
BA
and OE
AB
should be tied to V
CC
through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30
series resistors in both HIGH or
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay A
n
, B
n
to B
n
, A
n
C
L
= 30 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
4.0
3.1
8.0
4.0
ns
ns
pF
pF
C
I/O
C
I
C
PD
input/output capacitance
input capacitance
power dissipation capacitance per
latch
notes 1 and 2
outputs enabled
outputs disabled
21
3
pF
pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 74ALVCH162601DG | 功能描述:總線收發(fā)器 18-BIT UNIV BUS XCVR 3-STATE RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH162601DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit universal bus transceiver with 30 ohm termination resistor; 3-state |
| 74ALVCH162601DGG,1 | 功能描述:總線收發(fā)器 18-BIT UNIV BUS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH162601DGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVCH162601DGG,118 | 制造商:NXP Semiconductors 功能描述: |
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