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參數(shù)資料
| 型號(hào)： | 74ALVC74 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | 帶設(shè)置和復(fù)位功能的雙D觸發(fā)器；上升沿觸發(fā) |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74ALVC74 |
2003 May 26
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74ALVC74
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nCP to nQ, nQ
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
3.7
2.6
2.8
2.7
3.5
2.5
3.1
2.3
425
3.5
35
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
t
PHL
/t
PLH
propagation delay nSD, nRD to nQ, nQ
f
max
C
I
C
PD
maximum clock frequency
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
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| 74ALVC74BQ,115 | 功能描述:觸發(fā)器 DUAL D-TYPE POSITIVE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ALVC74BQ115 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVC74BQ-G | 功能描述:觸發(fā)器 DUAL D-TYPE POSITIVE EDGE-TRIG RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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