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參數(shù)資料
| 型號(hào)： | 74ALVC541 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal buffer/line driver; 3-state |
| 中文描述： | 八路緩沖器/線路驅(qū)動(dòng)器，3態(tài) |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 74ALVC541 |
2002 Feb 26
2
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state
74ALVC541
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS LOW power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds
≤
250 mA
ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
The 74ALVC541 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC541 is an octal non-inverting buffer/line driver
with 3-state bus compatible outputs. The 3-state outputs
are controlled by the output enable inputs OE
0
and OE
1
.
A HIGH on OE
n
causes the outputs to assume a
high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay inputs A
n
to Y
n
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.2
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.5
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.3
3.0
ns
ns
ns
ns
pF
pF
C
I
C
I/O
C
PD
input capacitance
input/output capacitance
power dissipation capacitance per buffer
3.5
3.5
V
CC
= 3.3 V; notes 1 and 2
outputs enable
outputs disabled
25
0
pF
pF
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