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參數(shù)資料
| 型號： | 74ALVC16834A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 18位注冊登記驅(qū)動程序倒置，使三態(tài) |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 74ALVC16834A |
Philips Semiconductors
Product specification
74ALVC16834A
18-bit registered driver with inverted register enable
(3-State)
2000 Mar 14
8
AC WAVEFORMS FOR V
CC
= 3.0 V TO 3.6 V AND
V
CC
= 2.7 V RANGE
V
M
= 1.5 V
V
X
= V
OL
+ 0.3 V
V
Y
= V
OH
– 0.3 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= 2.7 V
AC WAVEFORMS FOR V
CC
= 2.3 V TO 2.7 V AND
V
CC
< 2.3 V RANGE
V
M
= 0.5 V
V
X
= V
OL
+ 0.15 V
V
Y
= V
– 0.15 V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
A
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Y
OUTPUT
SH00132
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
V
M
V
M
V
M
SH00165
NOTE: V
M
= 0.5 V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 2. Latch enable input (LE) pulse width,
the latch enable input to output (Yn) propagation delays.
ééé
ééé
ééé
GND
éééééééé
éééééééé
éééééééé
An
INPUT
LE
INPUT
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
t
SU
V
V
I
GND
V
V
M
SH00166
Waveform 3. Data set-up and hold times
for the An input to the LE input
CP INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
1/f
MAX
SH00135
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 4. The clock (CP) to Yn propagation delays,
the clock pulse width and the maximum clock frequency.
V
I
GND
éééé
éééé
éééé
ééééééé
ééééééé
ééééééé
An INPUT
V
I
GND
V
OH
Yn OUTPUT
V
OL
CP INPUT
t
su
t
h
t
su
t
h
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
SH00136
V
M
V
M
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16834ADG | 功能描述:總線收發(fā)器 18-BIT REG DRVR W/INV REG RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16834ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit registered driver with inverted register enable 3-State |
| 74ALVC16834ADGG,11 | 功能描述:總線收發(fā)器 18-BIT REG DRVR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16834ADGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVC16834ADGG,118 | 制造商:NXP Semiconductors 功能描述: |
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