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參數(shù)資料
| 型號(hào)： | 74ALVC16373 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | CAP,ELEC,2200UF,20%,35V,RDL |
| 中文描述： | 低電壓16位透明鎖存器，在3.6V耐壓輸入和輸出 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 124K |
| 代理商： | 74ALVC16373 |
2005 Fairchild Semiconductor Corporation
DS500687
www.fairchildsemi.com
October 2001
Revised May 2005
7
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.1V to 3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(I
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Support live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
!
2000V
Machine model
!
200V
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
74ALVC16373GX
(Note 2)
74ALVC16373MTD
(Note 3)
Package Number
BGA54A
(Preliminary)
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVC16373GX | Triple 3-Input Positive-AND Gates 14-SSOP -40 to 85 |
| 74ALVC16373MTD | Triple 3-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 74ALVC16374 | Triple 3-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 74ALVC16374MTD | Triple 3-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 74ALVC16374GX | Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16373/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low-Voltage 1.8/2.5/3.3 V 16-Bit D-TYpe Flip-Flop |
| 74ALVC16373DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
| 74ALVC16373DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
| 74ALVC16373DT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| 74ALVC16373DTR | 功能描述:IC LATCH TRANSPRNT 16BIT 48TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 鎖銷 系列:74ALVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74VCX 邏輯類型:D 型透明鎖存器 電路:8:8 輸出類型:三態(tài) 電源電壓:1.8 V ~ 3.6 V 獨(dú)立電路:2 延遲時(shí)間 - 傳輸:1.5ns 輸出電流高，低:6mA，6mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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