參數(shù)資料
型號： 74ACTQ652SPC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Quiet Series⑩ Transceiver/Register
中文描述： ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24
封裝： 0.300 INCH, PLASTIC, MS-001, DIP-24
文件頁數(shù)： 5/9頁
文件大?。?/td> 104K
代理商： 74ACTQ652SPC
5
www.fairchildsemi.com
7
DC Electrical Characteristics
(Continued)
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
PDIP package.
Note 6:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 7:
Max number of data inputs (n) switching. (n
1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
AC Electrical Characteristics
Note 8:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any separate outputs of the same device. The spec-
ification applies to any output switching in the same direction, either HIGH-to-LOW (T
OSHL
) or LOW-to-HIGH (T
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
T
A
=
40
°
C to
+
85
°
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
ILD
Maximum LOW Level
5.0
1.2
0.8
V
(Note 5)(Note 7)
Dynamic Input Voltage
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Typ
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
Symbol
Parameter
(V)
Units
(Note 8)
5.0
Min
Max
Max
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
OSHL
t
OSLH
Maximum Clock Frequency
Propagation Delay
Clock to Bus
MHz
5.0
2.0
7.0
9.5
2.0
10.0
ns
Propagation Delay
Bus to Bus
Propagation Delay
5.0
2.0
6.5
9.0
2.0
9.5
ns
5.0
2.5
6.5
10.0
2.5
10.5
ns
SBA or SAB to A or B
Enable Time
OEBA to A (Note 8)
5.0
2.0
7.0
10.5
2.0
11.0
Disable Time
OEBA to A (Note 8)
Enable Time
5.0
1.0
5.0
8.0
1.0
8.5
ns
5.0
2.0
7.0
10.5
2.0
11.0
OEAB to B
Disable Time
OEAB to B
5.0
1.0
5.0
8.0
1.0
8.5
ns
Setup Time, HIGH or
LOW, Bus to Clock
Hold Time, HIGH or
5.0
3.0
3.0
ns
5.0
1.5
1.5
ns
LOW, Bus to Clock
Clock Pulse Width
5.0
4.0
4.0
ns
HIGH or LOW
Output to Output Skew (Note 9)
A to B, B to A or
5.0
0.5
1.0
1.0
ns
Clock to Output
Symbol
Parameter
Typ
Units
Conditions
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
4.5
54
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
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