參數(shù)資料
型號: 74ACQ657
廠商: Fairchild Semiconductor Corporation
英文描述: Quiet Series⑩ Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs
中文描述: 安靜系列⑩八路雙向收發(fā)器,8位奇偶發(fā)生器/檢測器和三態(tài)輸出
文件頁數(shù): 1/10頁
文件大?。?/td> 96K
代理商: 74ACQ657
2000 Fairchild Semiconductor Corporation
DS010636
www.fairchildsemi.com
January 1990
Revised September 2000
7
3
74ACQ657
74ACTQ657
Quiet Series
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The ACQ/ACTQ657 contains eight non-inverting buffers
with 3-STATE outputs and an 8-bit parity generator/
checker. Intended for bus oriented applications, the device
combines the 245 and the 280 functions in one package.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus or superior performance.
Features
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
I
Guaranteed pin-to-pin skew AC performance
I
Combines the 245 and the 280 functions in one package
I
300 mil 24-pin slim dual-in-line package
I
Outputs source/sink 24 mA
I
ACTQ has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
, Quiet Series
, FACT Quiet Series
, and GTO
are trademarks of Fairchild Semiconductor Corporation.
Order Number
74ACQ657SPC
74ACTQ657SC
74ACTQ657SPC
Package Number
N24C
M24B
N24C
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
A
0
A
7
B
0
B
7
T/R
OE
PARITY
ODD/EVEN
ERROR
Description
Data Inputs/3-STATE Outputs
Data Inputs/3-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/3-STATE Output
ODD/EVEN Parity Input
Error 3-STATE Output
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