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參數(shù)資料
| 型號： | 74ACT258SJX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low-Power µP Reset Circuits in 3-Pin SC70/SOT23 |
| 中文描述： | ACT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 90K |
| 代理商： | 74ACT258SJX |
www.fairchildsemi.com
2
7
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
The ACT258 is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I
0x
inputs are selected and when Select
is HIGH, the I
1x
inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The ACT258 is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Z
a
=
OE
(I
1a
S
+
I
0a
S)
Z
b
=
OE
(I
1b
S
+
I
0b
S)
Z
c
=
OE
(I
1c
S
+
I
0c
S)
Z
d
=
OE
(I
1d
S
+
I
0d
S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance state. If the outputs of the
3-STATE devices are tied together, all but one device must
be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Output
Select
Data
Outputs
Enable
Input
Inputs
OE
S
I
0
I
1
Z
H
X
X
X
Z
L
H
X
L
H
L
H
X
H
L
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