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參數(shù)資料
| 型號： | 74ACT18823SSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low-Power µP Reset Circuits in 3-Pin SC70/SOT23 |
| 中文描述： | ACT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 60K |
| 代理商： | 74ACT18823SSCX |
www.fairchildsemi.com
2
7
Functional Description
The ACT18823 consists of eighteen D-type edge-triggered
flip-flops. These have 3-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
device is byte controlled with each byte functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The follow-
ing description applies to each byte. The buffered clock
(CP
n
) and buffered Output Enable (OE
n
) are common to all
flip-flops within that byte. The flip-flops will store the state
of their individual D inputs that meet set-up and hold time
requirements on the LOW-to-HIGH CP
n
transition. With
OE
n
LOW, the contents of the flip-flops are available at the
outputs. When OE
n
is HIGH, the outputs go to the imped-
ance state. Operation of the OE
n
input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR
n
) and Clock Enable
(EN
n
) pins. These devices are ideal for parity bus interfac-
ing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Note 1:
The table represents the logic for one byte. The two bytes are inde-
pendent of each other and function identically.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
Inputs
Internal Output
Function
OE
CLR
EN
CP
I
n
Q
O
n
H
X
L
L
L
Z
High Z
H
X
L
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
Load
L
H
L
L
L
L
Load
L
H
L
H
H
H
Load
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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| 74ACT18825SSCX | Low-Power µP Reset Circuits in 3-Pin SC70/SOT23 |
| 74ACT18825MTD | 18-Bit Buffer/Line Driver with 3-STATE Outputs |
| 74ACT18825SSC | 18-Bit Buffer/Line Driver with 3-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ACT18825MTD | 功能描述:緩沖器和線路驅(qū)動器 18-Bit Buf/Line Drv RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT18825MTD_Q | 功能描述:緩沖器和線路驅(qū)動器 18-Bit Buf/Line Drv RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT18825MTDX | 功能描述:緩沖器和線路驅(qū)動器 18-Bit Buf/Line Drv RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT18825SSC | 功能描述:緩沖器和線路驅(qū)動器 18-Bit Buf/Line Drv RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT18825SSC_Q | 功能描述:緩沖器和線路驅(qū)動器 18-Bit Buf/Line Drv RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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