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參數(shù)資料
| 型號： | 74ACQT373QSC |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Quiet Series⑩ Octal Transparent Latch with 3-STATE Outputs |
| 中文描述： | 安靜系列⑩八路透明鎖存器與三態(tài)輸出 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 313K |
| 代理商： | 74ACQT373QSC |
tm
7
April 2007
1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
74ACQ373, 74ACTQ373
Quiet Series Octal Transparent Latch with 3-STATE
Outputs
Features
■
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch up immunity
Eight latches in a single package
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT373
CC
and I
OZ
reduced by 50%
■
■
■
■
■
■
■
General Description
The ACQ/ACTQ373 consists of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfy-
ing the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in the HIGH
impedance state.
The ACQ/ACTQ373 utilizes Fairchild Quiet Series
technology to guarantee quiet output switching and
improve dynamic threshold performance. features
GTO output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Order
Number
Package
Number
Package Description
74ACQ373SC
74ACQ373SJ
74ACTQ373SC
74ACTQ373SJ
74ACQT373QSC
M20B
M20D
M20B
M20D
MQA20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Pin Names
Description
D
LE
OE
O
0
–D
7
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
0
–O
7
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
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