參數(shù)資料
型號(hào)： 74ACQ657SPC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Quiet Series⑩ Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs
中文描述： AC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24
封裝： 0.300 INCH, SLIM, PLASTIC, MS-001, DIP-24
文件頁數(shù)： 6/10頁
文件大?。?/td> 96K
代理商： 74ACQ657SPC
www.fairchildsemi.com
6
7
AC Electrical Characteristics for ACQ
Note 13:
Voltage Range 3.3 is 3.3V
±
0.3V
Voltage Range 5.0 is 5.0V
±
0.5V
Note 14:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
Note 15:
These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuitry. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin
≥
(A to PARITY)
+
(Output
Enable Time).
V
CC
T
A
=
25
°
C
C
L
=
50 pF
Typ
8.0
5.0
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
2.5
1.5
Symbol
Parameter
(V)
Units
(Note 13)
3.3
5.0
Min
2.5
1.5
Max
11.5
7.5
Max
12.0
8.0
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Propagation Delay
A
n
to B
n
, B
n
to A
n
Propagation Delay
A
n
to Parity
Propagation Delay
ns
3.3
5.0
3.3
3.0
2.0
3.0
11.5
7.0
10.0
16.5
10.5
15.0
3.0
2.0
3.0
17.0
11.0
15.5
ns
ns
ODD/EVEN to PARITY
Propagation Delay
ODD/EVEN to ERROR
5.0
3.3
5.0
2.5
3.0
2.5
6.5
10.0
6.5
10.0
15.0
10.0
2.5
3.0
2.5
10.5
15.5
10.5
ns
Propagation Delay
B
n
to ERROR
Propagation Delay
3.3
5.0
3.3
3.5
2.5
3.0
11.5
7.0
9.0
16.0
10.5
13.5
3.5
2.5
3.0
16.5
11.0
14.0
ns
ns
PARITY to ERROR
Output Enable Time
OE to A
n
/B
n
Output Disable Time
OE to A
n
/B
n
Output Enable Time
5.0
3.3
5.0
2.0
2.5
2.0
6.0
9.0
6.0
9.0
13.5
9.0
2.0
2.5
2.0
9.5
14.0
9.5
ns
3.3
5.0
3.3
1.0
1.0
2.5
8.5
5.5
9.0
13.0
8.5
13.5
1.0
1.0
2.5
13.5
9.0
14.0
ns
ns
OE to ERROR (Note 15)
Output Disable Time
OE to ERROR
5.0
3.3
5.0
2.0
1.0
1.0
6.0
8.5
5.5
9.0
13.0
8.5
2.0
1.0
1.0
9.5
13.5
9.0
ns
Output Enable Time
OE to PARITY
Output Disable Time
3.3
5.0
3.3
2.5
2.0
1.0
9.0
6.0
8.5
13.5
9.0
13.0
2.5
2.0
1.0
14.0
9.5
13.5
ns
ns
OE to PARITY
Output to Output Skew (Note 14)
5.0
3.3
1.0
5.5
1.0
8.5
1.5
1.0
9.0
1.5
ns
A
n
, B
n
to B
n
, A
n
5.0
0.5
1.0
1.0
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