參數(shù)資料
型號： 73S1215F-EB
廠商： Maxim Integrated Products
文件頁數(shù)： 85/136頁
文件大小： 0K
描述： BOARD EVAL 73S1215F CBL/DOC/CD
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
系列： *
73S1215F Data Sheet
DS_1215F_003
1.7.8 Real-Time Clock with Hardware Watchdog (RTC)
Figure 9 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator
signal and divider logic to produce 0.5-second time marks. The time marks are used to create interrupts
at intervals from 0.5 seconds to 8 seconds as selected by RTC Interval (RTCINV(2:0)). The 32768Hz
oscillator can be disabled but is intended to operate at all times and in all power consumption modes.
If a 32kHz crystal is not provided, the 32kHz oscillator should be disabled and the RTC will operate from
MCLK (96MHz) divided by 2930 (refer to the oscillator and clock generation section). The clock
generated by the high speed oscillator will not yield exactly 32768 Hz, but a frequency of approximately
32764.505119 Hz. This yields a negative 106.6 PPM (1 / 9375) error with respect to 32768Hz. The RTC
circuit provides hardware to compensate for this error by providing an offset circuit that will adjust the
RTC counter.
d exactly 32768 Hz, but a frequency of approximately
32764.505119 Hz. This yields a negative 106.6 PPM (1 / 9375) error with respect to 32768Hz. The RTC
circuit provides hardware to compensate for this error by providing an offset circuit that will adjust the
RTC counter.
ADDER
23 BIT TRIM VALUE
24 BIT ACCUMULATOR
SELECT
INTERRUPT
RATE
DIVIDER
1/2 Second
1 Second
2 Second
4 Second
8 Second
SELECT
COUNT
RATE
32 BIT COUNTER
OVERFLOW
SIGN
ADVANCE
R/W BUS
R/
W
B
US
RTC INT
R/W BUS
R/W
BU
S
1/2
1
2
1/2
1
2
4
8
IF
overflow* sign=0, extra count
IF
overflow* sign=1, skip one count
1.024KHz
CLOCK
WATCH
DOG
TIMER
RESET
START
RTC ISR
WDT_TIMEOUT
1/2s TIMEOUT
RTCCLK
Figure 9: Real Time Clock Block Diagram
52
Rev. 1.4
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