參數(shù)資料
型號： 73S1210F-68M/F/PH
廠商： Maxim Integrated
文件頁數(shù)： 86/126頁
文件大?。?/td> 0K
描述： IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝： 260
系列： *
73S1210F Data Sheet
DS_1210F_001
62
Rev. 1.4
written into the KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from the
12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the MCLKCtl register (see the Oscillator
and Clock Generation section) to carry out scanning and debouncing. The keypad size can be adjusted
within the KSIZE register.
Normal scanning is performed by hardware when the SCNEN bit is set at 1 in the KSTAT register. Figure
13 shows the flowchart of how the hardware scanning operates. In order to minimize power, scanning
does not occur until a key-press is detected. Once hardware key scanning is enabled, the hardware
drives all column outputs low and waits for a low to be detected on one of the inputs. When a low is
detected on any row, and before key scanning starts, the hardware checks that the low level is still
detected after a debounce time. The debounce time is defined by firmware in the KSCAN register (bits
7:0, DBTIME). Debounce times from 4ms to 256ms in 4ms increments are supported. If a key is not
pressed after the debounce time, the hardware will go back to looking for any input to be low. If a key is
confirmed to be pressed, key scanning begins.
Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating
that a key is pressed at the intersection of the drive/sense line in the keypad. After all sense lines have
been checked without a key-press being detected, the next column line is asserted. The time between
checking each sense line is the scan time and is defined by firmware in the KSCAN register (bits 0:1 –
SCTIME). Scan times from 1ms to 4ms are supported. Scanning order does not affect the scan time.
This scanning continues until the entire keypad is scanned. If only one key is pressed, a valid key is
detected. Simultaneous key presses are not considered as valid (If two keys are pressed, no key is
reported to firmware).
Possible scrambling of the column scan order is provided by means of the KORDERL and KORDERH
registers that define the order of column scanning. Values in these registers must be updated every time
a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines.
The column and row intersection for the detected valid key are stored in the KCOL and KROW registers.
When a valid key is detected, an interrupt is generated. Firmware can then read those registers to
determine which key had been pressed. After reading the KCOL and KROW registers, the firmware can
update the KORDERL / KORDERH registers if a new scan order is needed. When the SCNEN bit is
enabled in the KSTAT register, the KCOL and KROW registers are only updated after a valid key has
been identified. The hardware does not wait for the firmware to service the interrupt in order to proceed
with the key scanning process. Once the valid key (or invalid key – e.g. two keys pressed) is detected,
the hardware waits for the key to be released. Once the key is released, the debounce timer is started. If
the key is not still released after the debounce time, the debounce counter starts again. After a key
release, all columns will be driven low as before and the process will repeat waiting for any key to be
pressed. When the SCNEN bit is disabled, all drive outputs are set to the value in the KCOL register. If
firmware clears the SCNEN bit in the middle of a key scan, the KCOL register contains the last value
stored in there which will then be reflected on the output pins. A bypass mode is provided so that the
firmware can do the key scanning manually (SCNEN bit must be cleared). In bypass mode, the firmware
writes/reads the Column and Row registers to perform the key scanning.
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73S1210F-68MR/F/PJ 功能描述:80515 73S12xx Microcontroller IC 8-Bit 24MHz 32KB (32K x 8) FLASH 68-QFN (8x8) 制造商:maxim integrated 系列:73S12xx 包裝:帶卷（TR） 零件狀態(tài):要求報(bào)價(jià) 核心處理器:80515 核心尺寸:8-位 速度:24MHz 連接性:I2C，智能卡，UART/USART 外設(shè):LED，POR，WDT I/O 數(shù):8 程序存儲容量:32KB（32K x 8） 程序存儲器類型:閃存 EEPROM 容量:- RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 6.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:68-VFQFN 裸露焊盤 供應(yīng)商器件封裝:68-QFN（8x8） 標(biāo)準(zhǔn)包裝:2,500
73S1210F-EB 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1210F-EB-Lite 功能描述:開發(fā)板和工具包 - 8051 73S1210F Eval Brd Lite w/Doc Cd, Cable RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
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