參數(shù)資料
型號(hào)： 73S1210F-68M/F/PH
廠商： Maxim Integrated
文件頁數(shù)： 119/126頁
文件大?。?/td> 0K
描述： IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝： 260
系列： *
73S1210F Data Sheet
DS_1210F_001
92
Rev. 1.4
Protocol Mode Register (SPrtcol): 0xFE0D
0x03
This register determines the protocol to be use when communicating with the selected smart card. This
register should be updated as required when switching between smart card interfaces.
Table 85: The SPrtcol Register
MSB
LSB
SCISYN
MOD9/8B
SCESYN
0
TMODE
CRCEN
CRCMS
RCVATR
Bit
Symbol
Function
SPrtcol.7
SCISYN
Smart Card Internal Synchronous mode - Configures internal smart card
interface for synchronous mode. This mode routes the internal interface
buffers for RST, IO, C4, C8 to the SCCtl register bits for direct firmware
control. CLK is generated by the ETU counter.
SPrtcol.6
MOD9/8B
Synchronous 8/9 bit mode select - For sync mode, in protocols with 9-bit
words, set this bit. The first eight bits read go into the RX FIFO and the
ninth bit read will be stored in the IO (or SIO) data bit of the SRXCtl register.
SPrtcol.5
SCESYN
Smart Card External Synchronous mode - Configures External Smart Card
interface for synchronous mode. This mode routes the external smart card
interface buffers for SIO to SCECtl register bits for direct firmware control.
SCLK is generated by the ETU counter.
SPrtcol.4
0
Reserved bit, must always be set to 0.
SPrtcol.3
TMODE
Protocol mode select - 0: T=0, 1: T=1. Determines which smart card
protocol is to be used during message processing.
SPrtcol.2
CRCEN
CRC Enable – 1 = Enabled, 0 = Disabled. Enables the checking/generation
of CRC/LRC while in T=1 mode. Has no effect in T=0 mode. If enabled and
a message is being transmitted to the smart card, the CRC/LRC will be
inserted into the message stream after the last TX byte is transmitted to the
smart card. If enabled, CRC/LRC will be checked on incoming messages
and the value made available to the firmware via the CRC LS/MS registers.
SPrtcol.1
CRCMS
CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking
algorithm to be used.
SPrtcol.0
RCVATR
Receive ATR – 1 = Enable ATR timeout, 0 = Disable ATR timeout. Set by
firmware after the smart card has been turned on and the hardware is
expecting ATR.
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