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| 型號(hào)： | 73M1903-EVM-WW |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 38/47頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 73M1903 PPU WORLDWIDE |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | * |
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DS_1903_032
73M1903 Data Sheet
Rev. 2.1
43
Example 2:
Fxtal = 18.432 MHz, Fref = 2.304 MHz.
Pdvsr = Integer [Fxtal/Fref] = 8 = 8h;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/2.304 = 8/1;
Pseq = {x,x,x,x,x,x,x,x} = xxh
Example 3:
Fxtal = 24.576 MHz, fref = 2.4576 MHz.
Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.4576 = 10/1;
Pseq = {x,x,x,x,x,x,x,x} = xxh
It is also important to note that when Fxtal/Fref is an integer the output of the pre-scaler is a straight
frequency divider (example 2). As such there will be no jitter generated at Fref. However if Fxtal/Fref is
a fractional number, Fref, at the output of the pre-scaler NCO would be exact only in an average sense
(example 1) and there will be a certain amount of fixed pattern (repeating) jitter associated with Fref which
can be filtered out by the PLL that follows by appropriately programming the PLL. It is important to note,
however, that the fixed pattern jitter does not degrade the performance of the sigma delta modulators so
long as its frequency is >> 4 kHz.
PLL
VCO
Kvco
NCO
Prescaler
PFD
Charge
Pump
NCO
Kd
Up
Dn
R1
C1
C2
Divide
by 2/1
Ichp Control
3
Fref
Kvco Control
Figure 18: PLL Block Diagram
1903B has a built in PLL circuit to allow an operation over wide range of Fs. It is of a conventional design
with the exception of an NCO based feedback divider. See Figure 18. The architecture of the 73m1903
dictates that the PLL output frequency, Fvco, be related to the sampling rate, fs, by fvco = 2 x 2304 x fs.
The nco must function as a divider whose divide ratio equals Fref/Fvco.
Just as in the NCO pre-scaler, a set of three numbers– Ndvsr (7 bits), Nrst (3 bit ) and Nseq (8 bits)
must be entered through a serial port to effect this divide:
Ndvsr = Integer [ Fref/Fxtal ] ;
Nrst = denominator of the ratio (Fvco/Fref), Dnco1, minus 1, when it is expressed as a ratio of two
smallest integers = Nnco1/Dnco1;
Nseq = Divide Sequence
Example 1:
Fs = 7.2 kHz or Fvco = 2 x 2304 x 7.2 kHz =33.1776 MHz, Fref = 1.728 MHz.
Ndvsr = Integer [ Fvco/Fref ] = 19
Nrst = 5 – 1 = 4 from Fvco/Fref = 19.2 = 96/5;
Nseq =
÷19, ÷19, ÷19, ÷19, ÷20 => {0,0,0,0,1} =xxx00001 = 01h.
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| 73M1903-IMR/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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