參數(shù)資料
型號(hào): 73M1903-EVM-WW
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 34/47頁(yè)
文件大小: 0K
描述: BOARD DEMO 73M1903 PPU WORLDWIDE
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: *
73M1903 Data Sheet
DS_1903_032
4
Rev. 2.1
1
Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Pin Name
Type
32QFN
Pin #
20VT
Pin#
Description
VND
GND
1,22
2,18
Negative Digital Ground
VNA
GND
16
13
Negative Analog Ground
VPD
PWR
2,25
3
Positive Digital Supply
VPA
PWR
10
8
Positive Analog Supply
VPPLL
PWR
20
17
Positive PLL Supply, shared with VPD
VNPLL
PWR
17
14
Negative PLL Ground
RST
I
9
7
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
OSCIN
I
19
16
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCOUT
O
18
15
Crystal oscillator circuit output pin.
GPIO(0-7)
I/O
3, 4, 5, 6,
23,
24,30,31
N/A
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
VREF
O
13
6
Reference voltage pin (Reflects VREF).
RXAP
I
15
12
Receive analog positive input.
RXAN
I
14
11
Receive analog negative input.
TXAP
O
12
10
Transmit analog positive output.
TXAN
O
11
9
Transmit analog negative output.
SCLK
O
8
5
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
SDOUT
O
32
1
Serial data output (or input to the host).
SDIN
I
29
20
Serial data input (or output from the host).
FS
O
7
4
Frame synchronization. (Active Low)
TYPE
I
27
19
Type of frame sync. Open, weak-pulled high = early
(mode1); tied low = late (mode0).
SckMode
I
28
NA
Controls the SCLK behavior after
FS. Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
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