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| 型號： | 73M1822-KEYCHN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 71/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD KEYCHAIN 73M1822 42-QFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
73
Auxiliary A/D Converter Status Bits
RNG
0x1A[7:0]
R
Result of Auxiliary A/D measuring the attenuated ring voltage.
Note: 1 lsb=1.31/128=~10.23 mV; 1’s compliment.
Example: 00100000
327 mV or Ring Voltage=32.7 V
LV
0x1B[7:1]
R
Line Voltage On and Off Hook
LV contains the seven most significant bits of an 8-bit A/D
representation of the voltage of the input of pin DCI. The voltage at
the DCI pin is equal to the decimal value of LV bits [7:1] x 21.87
mV. For example, if the value of 0100000 is read from LV bits
[7:1], this has a decimal value of 32, therefore DCI voltage equals
32 x 21.87 = 700 mV.
Note that the voltage at the DCI pin is the voltage divided by 5 (off
hook) or 100 (on hook). When offhook the diode bridge, switch
saturation voltage, etc. should also be added to calculate the
voltage at tip and ring.
LC
0x1C[7:1]
R
Loop Current in DC Path
Result of Auxiliary A/D measuring the Loop Current (7-bit
resolution, least significant bits only).
Note LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA; magnitude only.
The value of the resistor between the rectifier bridge and the DCS
pin is assumed to be 8.2
.
Example: 0000011
30.7 mV/RE=3.74 mA; 0010000 20 mA
Note: The AC path also has ~7 mA of loop current that should be
added to get the total loop current provided by the line.
Line Sensing Control
DET
0x03[2]
R
Detection of Voltage or Current Fault
0 = None of the three conditions is detected. (Default)
1 = Indicates the detection of one of three conditions:
Under Voltage, Over Voltage and Over Current.
This status bit is reset when read. This is a maskable interrupt. It
is enabled by the ENDET bit.
ENDET
0x05[2]
W
Enables Line Sensing Interrupt on Host Side Device
This bit controls whether an interrupt is generated based upon the
detection of Under Voltage, Over Voltage and Over Current.
0 = Disable detector interrupt. (Default)
1 = Enable detector interrupt.
ENDT
0x12[1]
WO
Enable Detectors on Line Side Device
0 = UVDT, OVDT and OIDT conditions are ignored. (Default)
1 = Enables UVDT, OVDT and OIDT in the Line-Side Device and
allows them to be used in the Host-Side Device.
Under-Voltage Detection Control and Status
ENUVD
0x15[2]
WO
Enable Under Voltage Detector on Line Side Device
1 = Under Voltage Detector Enabled. When enabled, the ENNOM
bit is temporarily set to the wide bandwidth mode if an
under-voltage condition detected to allow fast reacquisition of the
line.
UVDET
0x1E[6]
R
Under-Voltage Detection on Line Side Device
0 = Under Voltage condition is not detected at VPS. (Default)
1 = Under Voltage condition is detected at VPS.
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