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參數(shù)資料
| 型號： | 73M1822-KEYCHN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 67/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD KEYCHAIN 73M1822 42-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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DS_1x22_001
73M1822/73M1922 Data Sheet
Rev. 1.6
7
The Line-Side Device (73M1912 / 73M1822) consists of:
1. Digital Sigma Delta Modulator (DSDM)
2. Transmit Analog Front End (TxAFE)
3. Receive Analog Front End (RxAFE) including Sigma Delta Modulator (ASDM)
4. Sinc^3 Filter (Sinc3)
5. On-chip Line Interface Circuit (ONLIC)
6. Line-Side Barrier Interface Circuit (LSBI)
The transmit data (TxData) is interpolated up within TIF (Transmit Interpolation Filter) from the sampling
frequency (Fs) to twice the sampling frequency resulting in TxD.
Control information (CTL) is time-division multiplexed with TxD, serialized within MSBI, and sent across the
barrier to 73M1912 LIC (Line Interface Circuitry). This is then received and processed within LSBI and
separated into TxD and CTL. TxD is digitally sigma-delta modulated to form a serialized Transmit Bit
Stream (TBS). The TBS is D/A converted for final transmission to the line. CTL is used to control various
features of the Line-Side Device.
On the receive side, the received analog signal from the line is sigma-delta modulated to form a serialized
Receive Bit Stream (RBS). RBS is decimated down to twice the sampling frequency as RxD and
time-division multiplexed with status Information (STA) from the Auxiliary A/D regarding line condition in
LSBI block and transmitted to the Host-Side Device. The MSBI processes this data and separates it into
RxD and STA. Rxd is further decimated to down to Fs and sent to the host through the MAFE interface.
STA is sent to the host through the MAFE interface using a different time slot.
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