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參數(shù)資料
| 型號(hào)： | 73K212AL |
| 廠商： | TDK Corporation |
| 英文描述： | V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid |
| 中文描述： | .22，.21，貝爾212A章，貝爾103單芯片調(diào)制解調(diào)器集成混合 |
| 文件頁(yè)數(shù)： | 5/26頁(yè) |
| 文件大小： | 286K |
| 代理商： | 73K212AL |
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73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid
5
PIN DESCRIPTION
POWER
NAME
PIN
TYPE
DESCRIPTION
GND
1
I
System Ground
VDD
16
I
Power supply input, 5 V ±10%. Bypass with 0.1 and 22 μF capacitors to
GND.
VREF
31
O
An internally generated reference voltage. Bypass with 0.1 μF capacitor
to ground.
ISET
28
I
Chip current reference. Sets bias current for op-amps. The chip current is
set by connecting this pin to VDD through a 2 M
resistor. ISET should
be bypassed to GND with a 0.1 μF capacitor.
PARALLEL CONTROL INTERFACE
ALE
13
I
Address latch enable. The falling edge of ALE latches the address on
AD0-AD2 and the chip select on
CS
.
AD0-AD7
5-12
I/O
Tristate
Address/data bus. These bi-directional tri-state multiplexed lines carry
information to and from the internal registers.
CS
23
I
Chip select. A low on this pin during the falling edge of ALE allows a read
cycle or a write cycle to occur. AD0-AD7 will not be driven and no
registers will be written if
CS
(latched) is not active. The state of
CS
is
latched on the falling edge of ALE.
CLK
2
O
Output clock. This pin is selectable under processor control to be either
the crystal frequency (for use as a processor clock) or 16 times the data
rate for use as a baud rate clock in DPSK modes only. The pin defaults
to the crystal frequency on reset.
INT
20
O
Interrupt. This open drain output signal is used to inform the processor
that a detect flag has occurred. The processor must then read the detect
register to determine which detect triggered the interrupt.
INT
will stay low
until the processor reads the detect register or does a full reset.
RD
15
I
Read. A low requests a read of the 73K222BL internal registers. Data
cannot be output unless both
RD
and the latched
CS
are active or low.
RESET
30
I/with
Pulldown
Reset. An active high signal on this pin will put the chip into an inactive
state. All control register bits (CR0, CR1, Tone) will be reset. The output
of the CLK pin will be set to the crystal frequency. An internal pull-down
resistor permits power-on-reset using a capacitor to VDD.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 73K221AL | V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid |
| 73K222AL | V.22, V.21, Bell 212A, 103 Single-Chip Modem |
| 73K222AL-IGT | V.22, V.21, Bell 212A, 103 Single-Chip Modem |
| 73K222AL-IH | V.22, V.21, Bell 212A, 103 Single-Chip Modem |
| 73K222AL-IP | V.22, V.21, Bell 212A, 103 Single-Chip Modem |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K212-IP | 制造商:Silicon Systems Inc 功能描述:1.2 kbps DATA, MODEM, PQCC28 |
| 73K212L-IP | 制造商: 功能描述:73K212L-IP |
| 73K221AL | 制造商:TDK 制造商全稱(chēng):TDK Electronics 功能描述:V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid |
| 73K222AL | 制造商:TERIDIAN 制造商全稱(chēng):TERIDIAN 功能描述:Single-Chip Modem |
| 73K222AL-IGT | 制造商:TDK 制造商全稱(chēng):TDK Electronics 功能描述:V.22, V.21, Bell 212A, 103 Single-Chip Modem |
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