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參數(shù)資料
| 型號： | 7282L12PAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 1K X 9 BI-DIRECTIONAL FIFO, 12 ns, PDSO56 |
| 封裝： | GREEN, TSSOP-56 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 7282L12PAG |
4
COMMERCIALTEMPERATURERANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JANUARY 13, 2009
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS)
ResetisaccomplishedwhenevertheReset(
RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place. Both
the Read Enable (
R) and Write Enable (W) inputs must be in the HIGH
state during the window shown in Figure 2, (i.e., tRSS before the rising
edge of
RS) and should not change until tRSR after the rising edge of
RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS).
WRITE ENABLE (
W)
A write cycle is initiated on the falling edge of this input if the Full Flag (
FF)
isnotset.Dataset-upandholdtimesmustbeadheredtowithrespecttotherising
edge of the Write Enable (
W).DataisstoredintheRAMarraysequentiallyand
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (
HF)willbesettoLOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (
HF)isthenreset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read operation, the Full Flag
(
FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO is
full, the internal write pointer is blocked from
W, so external changes in Wwill
not affect the FIFO when it is full.
READ ENABLE (
R)
A read cycle is initiated on the falling edge of the Read Enable (
R)provided
the Empty Flag (
EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,
independent of any ongoing write operations. After Read Enable (
R) goes
HIGH, the Data Outputs (Q0– Q8) will return to a high impedance condition until
the next Read operation. When all data has been read from the FIFO, the Empty
Flag (
EF) will go LOW, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (
EF) will go HIGH
after tWEF and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
Rso external changes in Rwill not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT (
FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
groundedtoindicatethatitisthefirstloaded(seeOperatingModes). IntheSingle
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (
XI).
ThesedevicescanbemadetoretransmitdatawhentheRetransmitEnable
control(
RT)inputispulsedLOW. Aretransmitoperationwillsettheinternalread
pointer to the first location and will not affect the write pointer. Read Enable (
R)
andWriteEnable(
W)mustbeintheHIGHstateduringretransmit.Thisfeature
is useful when less than 256/512/1,024/2,048/4,096/8,192 writes are per-
formedbetweenresets.TheretransmitfeatureisnotcompatiblewiththeDepth
Expansion Mode and will affect the Half-Full Flag (
HF), depending on the
relative locations of the read and write pointers.
EXPANSION IN (
XI)
This input is a dual-purpose pin. Expansion In (
XI)isgroundedtoindicate
an operation in the single device mode. Expansion In (
XI) is connected to
Expansion Out (
XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG (
FF)
The Full Flag (
FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
write pointer is one location less than the read pointer, indicating that the
deviceisfull.IfthereadpointerisnotmovedafterReset(
RS),theFull-Flag(FF)
will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281, 1,024
writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for the
IDT7284 and 8,192 writes for the IDT7285.
EMPTY FLAG (
EF)
The Empty Flag (
EF)willgoLOW,inhibitingfurtherreadoperations,when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG (
XO/HF)
This is a dual-purpose output. In the single device mode, when Expan-
sion In (
XI)isgrounded,thisoutputactsasanindicationofahalf-fullmemory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (
HF) will be set LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal
toonehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(
HF)isthenreset
by using rising edge of the read operation.
IntheDepthExpansionMode,ExpansionIn(
XI)isconnectedtoExpansion
Out (
XO)ofthepreviousdevice.Thisoutputactsasasignaltothenextdevice
in the Daisy Chain by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (
R) is in a HIGH state.
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| 7282L12PAG8 | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7282L15PA | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7282L15PA8 | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度: 總線定向: 存儲容量: 定時類型: 組織: 最大時鐘頻率: 訪問時間: 電源電壓-最大: 電源電壓-最小: 最大工作電流: 最大工作溫度: 封裝 / 箱體: 封裝: |
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| 7282L15PAGI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 1K x 9 56-Pin TSSOP T/R |
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