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參數(shù)資料
| 型號： | 723631L15PF9 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 512 X 36 OTHER FIFO, 11 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 723631L15PF9 |
12
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1,024 x 36 and 2,048 x 36
When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB
edge loads the current read pointer with the shadow read-pointer value
and the OR flag reflects the new level of fill immediately. If the retransmit
changes the FIFO status out of the almost-empty range, up to two CLKB
rising edges after the retransmit cycle are needed to switch
AE high (see
Figure 12). The rising CLKB edge that takes the FIFO out of retransmit
mode shifts the read pointer used by the IR and
AF flags from the shadow
to the current read pointer. If the change of read pointer used by IR and
AF should cause one or both flags to transmit HIGH, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A
rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of IR if it occurs at time tSKEW1 or greater after the
rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO is
taken out of retransmit mode is the first synchronizing cycle of
AF if it occurs
at time tSKEW2 or greater after the rising CLKB edge (see Figure 14).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723631/723641/723651 to
pass command and control information between port A and port B. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
FIFO for a port data transfer operation. A LOW-to-HIGH transition on
CLKA writes A0-A35 data to the mail1 register when a port-A Write is
selected by
CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH
transition on CLKB writes B0-B35 data to the mail2 register when a port-B
Write is selected by
CSB, W/RB, and ENB with MBB HIGH. Writing data to
a mail register sets its corresponding flag (
MBF1 or MBF2) LOW.
Attempted writes to a mail register are ignored while its mail flag is LOW.
When the port-B data (B0-B35) outputs are active, the data on the bus
comes from the FIFO output register when the port-B Mailbox select (MBB)
input is LOW and from the Mail1 register when MBB is HIGH. Mail2 data is
always present on the port-A data (A0-A35) outputs when they are active.
The Mail1 register Flag (
MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a port-B Read is selected by
CSB, W/RB, and ENB with
MBB HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a port-A Read is selected by
CSA, W/RA,
and ENA with MBA HIGH. The data in a mail register remains intact after it
is read and changes only when new data is written to the register. Mail
Register and Mail Register Flag timing can be found in Figure 15
and 16.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 723631L15PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO - Bulk |
| 723631L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO - Tape and Reel |
| 723631L15PQF | 功能描述:IC FIFO SYNC 512X36 132QFP 制造商:idt, integrated device technology inc 系列:7200 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時間:11ns 電壓 - 電源:4.5 V ~ 5.5 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴充類型:深度，寬度 可編程標志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:132-BQFP 緩沖式 供應商器件封裝:132-PQFP（24.13x24.13） 標準包裝:36 |
| 723631L20PF | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP |
| 723631L20PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP T/R |
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