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| 型號： | 709279L9PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 32K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 314K |
| 代理商： | 709279L9PF8 |
6.42
IDT709279/69S/L
Preliminary
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
Timing Waveform of Flow-ThroughRead-to-Write-to-Read (OEControlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
3243 drw 13
Qn
DATAOUT
CE1
UB, LB
tCD1
Qn + 1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
tCKHZ
Qn + 3
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
NOP
READ
tCKLZ
(4)
(2)
(1)
tSW tHW
WRITE
(5)
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
(4)
DATAIN
Dn + 2
CE0
CLK
3243 drw 14
Qn
DATAOUT
CE1
UB, LB
tCD1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
Qn + 4
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
WRITE
READ
tCKLZ
(2)
Dn + 3
tOHZ
(1)
tSW tHW
OE
tOE
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| IDT709279L12PFI8 | 32K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 |
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| 70C100BIL | 110 A, SCR, TO-209AC |
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