參數(shù)資料
型號: 6PAIC3106IRGZRQ1
廠商: Texas Instruments
文件頁數(shù): 26/103頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO 48-QFN
標準包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 92 / 102(差分),92 / 95(單端)
動態(tài)范圍,標準 ADC / DAC (db): 91 / 99(差分),91 / 92(單端)
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(7x7)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1077 (CN2011-ZH PDF)
其它名稱: 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
NOTE
When NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode,
MCLK can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz.
When the PLL is enabled,
fS(ref) = (PLLCLK_IN × K × R) / (2048 × P), where
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz
≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz
≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4
≤ J ≤ 55
When the PLL is enabled and D
≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz
≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz
≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4
≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Table 3 lists several example cases of typical MCLK rates and how to program the PLL to achieve
fS(ref) = 44.1 kHz or 48 kHz.
Table 3. Typical MCLK Rates
fS(ref) = 44.1 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
2.8224
1
32
0
44100.00
0.0000
5.6448
1
16
0
44100.00
0.0000
12.0
1
7
5264
44100.00
0.0000
13.0
1
6
9474
44099.71
–0.0007
16.0
1
5
6448
44100.00
0.0000
19.2
1
4
7040
44100.00
0.0000
Copyright 2009–2012, Texas Instruments Incorporated
29
Product Folder Links: TLV320AIC3106-Q1
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