- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369230 > 68HRC05J5A (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 68HRC05J5A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 75/106頁(yè) |
| 文件大?。?/td> | 1069K |
| 代理商： | 68HRC05J5A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INSTRUCTION SET
MOTOROLA
10-7
10.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing.
Table 10-4
lists these instructions.
10.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in
Table 10-5
, use inherent addressing.
Table 10-4. Bit Manipulation Instructions
Instruction
Mnemonic
Clear Bit
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Set Bit
BSET
Table 10-5. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 68HRC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05K0 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05PL4 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05PL4B | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705PL4 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 68HRC705JJ7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| 68HRC705JP7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| 68HRC705SJ7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| 68HRC705SP7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| 68J0313 | 制造商:n/a 功能描述:HEADSET,MONO,CR VCE TUBE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。