
Pulse-Width Modulator for Motor Control (PWMMC)
Control Logic Block
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
Advance Information
MOTOROLA
Pulse-Width Modulator for Motor Control (PWMMC)
181
FTACK4
—
Fault Acknowledge 4 Bit
The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG4. Writing a
0 will have no effect.
FTACK3
—
Fault Acknowledge 3 Bit
The FTACK3 bit is used to acknowledge and clear FFLAG3. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG3. Writing a
0 will have no effect.
FTACK2
—
Fault Acknowledge 2 Bit
The FTACK2 bit is used to acknowledge and clear FFLAG2. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG2. Writing a
0 will have no effect.
FTACK1
—
Fault Acknowledge 1 Bit
The FTACK1 bit is used to acknowledge and clear FFLAG1. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG1. Writing a
0 will have no effect.
DT6
—
Dead-Time 6 Bit
Current sensing pin IS3 is monitored immediately before dead-time
ends due to the assertion of PWM6.
DT5
—
Dead-Time 5 Bit
Current sensing pin IS3 is monitored immediately before dead-time
ends due to the assertion of PWM5.
DT4
—
Dead-Time 4 Bit
Current sensing pin IS2 is monitored immediately before dead-time
ends due to the assertion of PWM4.
DT3
—
Dead-Time 3 Bit
Current sensing pin IS2 is monitored immediately before dead-time
ends due to the assertion of PWM3.
DT2
—
Dead-Time 2 Bit
Current sensing pin IS1 is monitored immediately before dead-time
ends due to the assertion of PWM2.
DT1
—
Dead-Time 1 Bit
Current sensing pin IS1 is monitored immediately before dead-time
ends due to the assertion of PWM1.