
Electrical Specifications
Technical Data
MC68HC08AZ32A — Rev 1.0
434
Electrical Specifications
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MOTOROLA
24.11 CGM Acquisition/Lock Time Information
Description
Symbol
Min
Typ
Max
Unit
Notes
Manual Mode Time to Stable
t
ACQ
—
(8 x V
DDA
) /
(f
CGMXCLK
x K
ACQ)
—
s
If C
F
Chosen
Correctly
Manual Stable to Lock Time
t
AL
—
(4 x V
DDA
) /
(f
CGMXCLK
x K
TRK
)
—
s
If C
F
Chosen
Correctly
Manual Acquisition Time
t
LOCK
—
t
ACQ
+t
AL
—
s
Tracking Mode Entry
Frequency Tolerance
D
TRK
0
—
±
3.6
%
Acquisition Mode Entry
Frequency Tolerance
D
UNT
±
6.3
—
±
7.2
%
LOCK Entry Freq. Tolerance
D
LOCK
0
—
±
0.9
%
LOCK Exit Freq. Tolerance
D
UNL
±
0.9
—
±
1.8
%
Reference Cycles per
Acquisition Mode
Measurement
n
ACQ
—
32
—
—
Reference Cycles per
Tracking Mode
Measurement
n
TRK
—
128
—
—
Automatic Mode Time
to Stable
t
ACQ
n
ACQ
/f
CGM
XCLK
(8 x V
DDA
) /
(f
CGMXCLK
x K
ACQ)
s
If C
F
Chosen
Correctly
Automatic Stable to Lock
Time
t
AL
n
TRK
/f
CGM
XCLK
(4 x V
DDA
) /
(f
CGMXCLK
x K
TRK
)
—
s
If C
F
Chosen
Correctly
Automatic Lock Time
t
LOCK
—
0.65
25
ms
PLL Jitter, Deviation of
Average Bus Frequency
over 2 ms (note 1)
0
—
±
(f
CRYS
)
x (.025%)
x (N/4)
%
N = VCO
Freq. Mult.
K value for automatic mode
time to stable
K
acq
—
0.2
—
—
K value
K
trk
—
0.004
—
—
NOTES:
1. Guaranteed but not tested.
2. V
DD
= 5.0 Vdc ± 0.5 V, V
SS
= 0 Vdc, T
A
= -40C to T
A
(MAX), unless otherwise noted.
3. Conditions for typical and maximum values are for Run mode with f
CGMXCLK
= 8MHz, f
BUSDES
= 8MHz, N = 4, L = 7,
discharged C
F
= 15 nF, V
DD
= 5Vdc.
4. Refer to Phase-Locked Loop (PLL) section for guidance on the use of the PLL.
F
Freescale Semiconductor, Inc.
n
.