
Clock Generator Module (CGM)
Technical Data
MC68HC08AZ32A — Rev 1.0
136
Clock Generator Module (CGM)
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MOTOROLA
NOTE:
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
f
VRS
. (See
Circuits
on page 121,
Programming the PLL
on page
125, and
PLL Control Register
on page 131.) VRS7–VRS4 cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. See
Special Programming Exceptions
on page 127. A value of
$0 in the VCO range select bits disables the PLL and clears the BCS
bit in the PCTL. (See
Base Clock Selector Circuit
on page 127 and
Special Programming Exceptions
on page 127 for more
information.) Reset initializes the bits to $6 to give a default range
multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
Table 8-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
1
0001
1
0010
2
0011
3
1101
13
1110
14
1111
15
F
Freescale Semiconductor, Inc.
n
.