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參數(shù)資料
| 型號(hào)： | 668-0003-C |
| 廠商： | Rabbit Semiconductor |
| 文件頁數(shù)： | 47/228頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU RABBIT2000 30MHZ 100PQFP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Rabbit 2000 |
| 處理器類型： | Rabbit 2000 8-位 |
| 速度： | 30MHz |
| 電壓： | 2.7V，3V，3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 316-1004 668-0003 |
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134
Rabbit 2000 Microprocessor User’s Manual
applications such as Modbus require controlling gaps between characters. Thus, it would
be inadvisable to attempt Modbus with parity at a high data rate.
Other ways to add a 1-baud delay are listed below:
Use another serial port as a timer. Disable the interrupts on the port being used to trans-
mit and, at the same time the data register is loaded, load a dummy character and a 9th
bit in the other serial port. The interrupt in the auxiliary port will occur after 11 baud
times rather than 10 baud times, thus guaranteeing the stop bit its full time.
Send a full dummy character to create a very long stop bit. To avoid the long stop bit,
the baud timer can be speeded up while the dummy character is sent to reduce the
length of the extra stop bit. The synchronous nature of timers A4–A7 allows the divide
ratio to be increased or decreased at will without generating irregular clock pulses.
Use a timer interrupt to generate the extra 1-baud delay between characters. The inter-
rupts can be enabled for the same timer that was used to generate the baud clock, and
the timer can be slowed down so that one cycle is equal to the delay length needed.
Use serial ports A and B, which have synchronous capability, to send a character in
synchronous mode (output Tx disabled). The synchronous character is sent at a baud
rate 8 times greater than the asynchronous baud rate, giving an additional baud time.
For this to work, the pin used for the synchronous clock out (port B bits 0 or 1) must
either be unconnected or connected to something that can tolerate a burst of 8 clock
pulses.
12.7.6 Supporting 9th Bit Communication Protocols
This section describes how 9th bit communication protocols work. 9th bit communication
protocols are supported by processors such as the 8051 and the Z180, and by companies
such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a
parity bit would normally be placed. Requests from the network master to one of its slaves
consist of a frame of bytes—the first byte has the 9th bit set to "1" (as the signal is
observed at the Tx pin of the processor) and the following bytes have the 9th bit set to "0."
The first byte is identified as the address byte, which specifies the slave unit where the
message is directed. This enables a slave to find the start of a message, which is the byte
with the 9th bit set, and to determine if the message is directed to it. If the message is
directed to a particular slave, the slave will then read the characters in the rest of the mes-
sage; otherwise the slave will continue to scan for a start of message character containing
its address.
Normally the 9th bit is set to "1" only on the first byte of a request transmitted by the net-
work master. The subsequent bytes and the slave replies have the 9th bit set to zero. Since
the majority of the traffic has a 9th bit set low, it is only necessary to stretch the stop bit for
the first bytes or address bytes. This can be done without sacrificing performance by send-
ing a dummy character (transmitter disconnected) after the address byte.
Some microprocessor serial ports have a “wake up” mode of operation. In this mode, char-
acters without the 9th bit set to "1" are ignored, and no interrupt is generated. When the
start of a frame is detected, an interrupt takes place on that byte. If the byte contains the
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